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| 1. general description the dac1008d650 is a high-speed 10-bit dual channel digital-to-analog converter (dac) with selectable 2 , 4 or 8 interpolating filters optimi zed for multi-carrier wcdma transmitters. because of its digital on-chip modulation, the dac1008d650 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to if. the mixing frequency is adjusted via a serial peripheral interface (spi) with a 32-bit numerically controlled oscillato r (nco) and the phase is controlled by a 16-bit register. the dac1008d650 also includes a 2 , 4 or 8 clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current. the input data format is serial according to jesd204a specificatio n. this new interface has numerous advantages over the traditional parallel one: easy pcb layout, lower radiated noise, lower pin count, self-synchro nous link, skew compensation. the maximum number of lanes of the dac1008d650 is 4 and its maximum serial data rate is 3.125 gbps. the multiple device synchron ization (mds) guarantees a maximum skew of one output clock period between several dac devices. md s incorporates modes: master/slave and all slave mode. 2. features and benefits dac1008d650 dual 10-bit dac; up to 650 msps; 2 , 4 or 8 interpolating with jesd204a interface rev. 2 ? 17 december 2010 product data sheet ? dual 10-bit resolution ? imd3: 80 dbc; f s =640msps; f o = 140 mhz ? 650 msps maximum update rate ? acpr: 64 dbc; two carriers wcdma; f s = 640 msps; f o = 133 mhz ? selectable 2 , 4 or 8 interpolation filters ? typical 1.20 w power dissipation at 4 interpolation, pll off and 640 msps ? input data rate up to 312.5 msps ? power-down mode and sleep modes ? very low noise cap free integrated pll ? differential scalable output current from 1.6 ma to 22 ma ? 32-bit programmable nco frequency ? on-chip 1.25 v reference ? four jesd204a serial input lanes ? external analog offset control (10-bit auxiliary dacs) ? 1.8 v and 3.3 v power supplies ? internal digital offset control ? lvds compatible clock inputs ? inverse (sin x) / x function
dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 2 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 3. applications ? wireless infrastructure: lte, wim ax, gsm, cdma, wcdma, td-scdma ? communication: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? broadband wireless systems ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information ? two?s complement or binary offset data format ? fully compatible spi port ? lmf = 421 or lmf = 211 support ? industrial temperature range from ? 40 cto+85 c ? differential cml receiver with embedded termination ? integrated pll can be bypassed ? synchronization of multiple dac outputs ? embedded complex modulator table 1. ordering information type number package name description version DAC1008D650HN hvqfn64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 9 0.85 mm sot804-3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 3 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 5. block diagram fig 1. block diagram 005aaa160 ioutbp ioutbn ioutap ioutan auxap auxan sin cos + offset control q dac single side band modulator x sin x vires gapout + x sin x 10-bit gain control 10-bit offset control nco 32-bit frequency setting 16-bit phase adjustment 10-bit gain control ref. bandgap and biasing i dac aux. dac auxbp auxbn 10-bit offset control aux. dac 2 fir 2 2 fir 1 multi-dac synchronization 2 fir 2 2 fir 3 2 fir 3 2 fir 1 clock generator unit vin_p3 vin_n3 digital layer processing jesd204a spi control registers sdo sdio scs_n sclk clkinp clkinn mds_p mds_n vin_p2 vin_n2 vin_p1 vin_n1 vin_p0 l0 l1 l2 l3 vin_n0 sync_outp sync_outn inter lane alignment lane proc reset_n DAC1008D650HN lane proc lane proc lane proc frame assembly dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 4 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration 005aaa155 DAC1008D650HN transparent top view agnd v dda(3v3) agnd v dda(3v3) auxbp auxap auxbn auxan agnd agnd v dda(1v8) v dda(1v8) v dda(1v8) v dda(1v8) gapout agnd vires clkinp n.c. clkinn reset_n agnd scs_n v dda(1v8) v ddd(1v8) mds_p sclk mds_n sdio v ddd(1v8) sdo n.c. v dda(1v8) agnd v dda(1v8) v dda(1v8) agnd ioutbn ioutbp agnd agnd ioutap ioutan agnd v dda(1v8) v dda(1v8) agnd v dda(1v8) jtag n.c. n.c. vin_n3 vin_p3 v ddd(1v8) vin_p2 vin_n2 vin_n1 vin_p1 v ddd(1v8) vin_p0 vin_n0 sync_outp sync_outn v ddd(1v8) 16 33 15 34 14 35 13 36 12 37 11 38 10 39 9 40 8 41 7 42 6 43 5 44 4 45 3 46 2 47 1 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 terminal 1 index area table 2. pin description symbol pin type [1] description sdo 1 o spi data output sdio 2 i/o spi data input/output sclk 3 i spi clock v ddd(1v8) 4 p digital supply voltage 1.8 v scs_n 5 i spi chip se lect (active low) reset_n 6 i general reset (active low) n.c. 7 - not connected vires 8 i/o dac biasing resistor gapout 9 i/o bandgap input/output voltage v dda(1v8) 10 p analog supply voltage 1.8 v v dda(1v8) 11 p analog supply voltage 1.8 v dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 5 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a agnd 12 g analog ground auxbn 13 o complementary auxiliary dac b output auxbp 14 o auxiliary dac b output v dda(3v3) 15 p analog supply voltage 3.3 v agnd 16 g analog ground v dda(1v8) 17 p analog supply voltage 1.8 v agnd 18 g analog ground v dda(1v8) 19 p analog supply voltage 1.8 v v dda(1v8) 20 p analog supply voltage 1.8 v agnd 21 g analog ground ioutbn 22 o complementary dac b output current ioutbp 23 o dac b output current agnd 24 g analog ground agnd 25 g analog ground ioutap 26 o dac a output current ioutan 27 o complementary dac a output current agnd 28 g analog ground v dda(1v8) 29 p analog supply voltage 1.8 v v dda(1v8) 30 p analog supply voltage 1.8 v agnd 31 g analog ground v dda(1v8) 32 p analog supply voltage 1.8 v agnd 33 g analog ground v dda(3v3) 34 p analog supply voltage 3.3 v auxap 35 o auxiliary dac a output current auxan 36 o complementary auxiliary dac a output current agnd 37 g analog ground v dda(1v8) 38 p analog supply voltage 1.8 v v dda(1v8) 39 p analog supply voltage 1.8 v agnd 40 g analog ground clkinp 41 i clock input clkinn 42 i complementary clock input agnd 43 g analog ground v dda(1v8) 44 p analog supply voltage 1.8 v mds_p 45 i/o multi-devi ce synchronization mds_n 46 i/o complementary multi-device synchronization v ddd(1v8) 47 p digital supply voltage 1.8 v n.c. 48 - not connected v ddd(1v8) 49 p digital supply voltage 1.8 v sync_outn 50 o synchronization request to transmitter, complementary output sync_outp 51 o synchronization request to transmitter table 2. pin description ?continued symbol pin type [1] description dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 6 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a [1] p: power supply; g: ground; i: input; o: output. [2] h = heatsink (exposed die pad to be soldered to gnd. a minimum of 81 thermal vias are required). 7. limiting values 8. thermal characteristics [1] complies with jedec test board, in free air. vin_n0 52 i serial interface lane 0 negative input vin_p0 53 i serial interface lane 0 positive input v ddd(1v8) 54 p digital supply voltage 1.8 v vin_p1 55 i serial interface lane 1 positive input vin_n1 56 i serial interface lane 1 negative input vin_n2 57 i serial interface lane 2 negative input vin_p2 58 i serial interface lane 2 positive input v ddd(1v8) 59 p digital supply voltage 1.8 v vin_p3 60 i serial interface lane 3 positive input vin_n3 61 i serial interface lane 3 negative input n.c. 62 - not connected n.c. 63 - not connected jtag 64 i jtag test mode select (must be grounded) gnd h [2] g ground table 2. pin description ?continued symbol pin type [1] description table 3. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v dda(1v8) analog supply voltage (1.8 v) ? 0.5 +2.5 v v ddd digital supply voltage ? 0.5 +2.5 v t stg storage temperature ? 55 +150 c t amb ambient temperature ? 40 +85 c t j junction temperature ? 40 +125 c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 18.7 k/w r th(j-c) thermal resistance from junction to case [1] 6.7 k/w dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 7 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 9. characteristics table 5. characteristics v dda(1v8) =v ddd = 1.7 v to 1.9 v; v dda(3v3) = 3.13 v to 3.47 v; agnd and gnd are shorted together; t amb = ? 40 c to +85 c; typical values measured at v dda(1v8) =v ddd =1.8v; v dda(3v3) =3.3v; t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit v dda(3v3) analog supply voltage (3.3 v) i 3.13 3.3 3.47 v v ddd(1v8) digital supply voltage (1.8 v) i 1.7 1.8 1.9 v v dda(1v8) analog supply voltage (1.8 v) i 1.7 1.8 1.9 v i dda(3v3) analog supply current (3.3 v) f o =19mhz; f s = 640 msps; 4 interpolation; nco on i-41-ma i ddd(1v8) digital supply current (1.8 v) f o =19mhz; f s = 640 msps; 4 interpolation; nco on i-356-ma i dda(1v8) analog supply current (1.8 v) f o =19mhz; f s = 640 msps; 4 interpolation; nco on i - 373 - ma i ddd digital supply current difference x/sin x function on; f s =640msps i-48-ma p tot total power dissipation f s =640msps; 4 interpolation; nco off; dac q off c - 0.75 - w f s =640msps; 4 interpolation; nco off c - 1.20 - w f s =640msps; 4 interpolation; nco on c - 1.45 - w f s =625msps; 2 interpolation; nco off c - 1.29 - w f s =625msps; 2 interpolation; nco on c - 1.46 - w power-down mode; f o =19mhz; f s =640msps; 4 interpolation; nco on complete device; power-down mode i - 0.04 - w dac a and dac b; power-down mode i - 0.58 - w dac a and dac b; sleep mode i - 0.75 - w timing specifications t d(startup) start-up delay time from full power-down mode d - 20 - ms t d(restart) restart delay time from sleep mode d - 300 - ns t lock lock time maximum input rate d [2] -11- s clock inputs (clkinn, clkinp) [3] v i input voltage range: clk+ or clk ? | v gpd | <50mv [4] c 825 - 1575 mv dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 8 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a v idth input differential threshold voltage | v gpd | < 50 mv [4] c ? 100 - +100 mv r i input resistance d - 10 - m c i input capacitance d - 0.5 - pf digital inputs (sdo, sdio, sclk, scs_n, reset_n) v il low-level input voltage cgnd-0.3v ddd v v ih high-level input voltage c0.7v ddd -v ddd v i il low-level input current v il =0.3v ddd vi-1- a i ih high-level input current v ih =0.7v ddd vi-1- a digital outputs (sdo, sdio) v ol low-level output voltage i load =2ma c gnd - 0.13 v v oh high-level output voltage i load =2ma c 1.65 - v ddd v digital inputs (vin_p/vin_n) [5] v i(cm) common-mode input voltage d - 0.78 - v v i(dif)(p-p) peak-to-peak differential input voltage d 175 - 1000 mv z tt v tt source impedance d - 0.7 - z i differential input impedance d - 100 - digital outputs (sync_outn/sync_outp) [6] v o(cm) common-mode output voltage c-1.18-v v o(dif)(p-p) peak-to-peak differential output voltage c-0.45-v digital inputs/outputs (mds_n/mds_p) v o(dif)(p-p) peak-to-peak differential output voltage d - 600 - mv c o(l) output load capacitance between pins gnd and mds_n or mds_p d--10pf c i input capacitance between pins gnd and mds_n or mds_p d - 0.3 - pf table 5. characteristics ?continued v dda(1v8) =v ddd = 1.7 v to 1.9 v; v dda(3v3) = 3.13 v to 3.47 v; agnd and gnd are shorted together; t amb = ? 40 c to +85 c; typical values measured at v dda(1v8) =v ddd =1.8v; v dda(3v3) =3.3v; t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 9 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a analog outputs (ioutap, ioutan, ioutbp, ioutbn) i o(fs) full-scale output current register value = 00h (see ta b l e 1 3 and table 14 ) d-1.6-ma register = default value (see ta b l e 1 3 and table 14 ) -20- ma v o output voltage compliance range d 1.8 - v dda(3v3) v r o output resistance d - 250 - k c o output capacitance d - 3 - pf e o offset error variation c - 6 - ppm/ c e g gain error variation c - 18 - ppm/ c reference voltage output (gapout) v o(ref) reference output voltage c 1.20 1.25 1.29 v i o(ref) reference output current external voltage 1.2 v c - 40 - a v o(ref) reference output voltage variation c-117-ppm/ c analog auxiliary outputs ( auxap, auxan, auxbp and auxbn) i o(aux) auxiliary output current differential outputs i - 2.2 - ma v o(aux) auxiliary output voltage compliance range d 0 - 2 v n dac(aux)mono auxiliary dac monotonicity guaranteed d - 10 - bits input timing (vin_p/vin_n) f data data rate 2 interpolation d - - 312.5 msps 4 interpolation d - - 162.5 msps 8 interpolation d - - 81.25 msps f bit bit rate serial input d 0.7 - 3.125 gbps output timing (ioutap, ioutan, ioutbp, ioutbn) f s sampling rate d - - 650 msps t s settling time up to 0.5 lsb d - 20 - ns nco frequency range; f s = 650 msps f nco nco frequency register value = 00000000h (see ta b l e 2 1 to table 24 ) d-0-mhz register value = ffffffffh (see ta b l e 2 1 to table 24 ) d - 650 - mhz f step step frequency d - 0.151 - hz low power nco frequency range; f s = 650 msps f nco nco frequency reg value = 00000000h (see ta b l e 2 1 to table 24 ) d-0-mhz reg value = f8000000h (see ta b l e 2 1 to table 24 ) d - 630 - mhz table 5. characteristics ?continued v dda(1v8) =v ddd = 1.7 v to 1.9 v; v dda(3v3) = 3.13 v to 3.47 v; agnd and gnd are shorted together; t amb = ? 40 c to +85 c; typical values measured at v dda(1v8) =v ddd =1.8v; v dda(3v3) =3.3v; t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 10 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a f step step frequency d - 20.3 - mhz dynamic performances sfdr spurious-free dynamic range f data = 80 msps; f s =640msps; 8; bw = f data / 2; pll on f o = 4 mhz at ? 1dbfs c - 77 - dbc f data =160msps; f s =640msps; 4; bw = f data /2 f o =19mhz at ? 1dbfs c - 74 - dbc f data = 312.5 msps; f s =625msps; 2; bw = f data /2 f o =19mhz at ? 1dbfs i - 75 - dbc sfdr rbw restricted bandwidth spurious-free dynamic range f s =640msps; 4 interpolation; f o = 133 mhz at ? 1 dbfs; bw = 100 mhz i-81-dbc f s =640msps; 4 interpolation; f o = 133 mhz at ? 1 dbfs; bw = 20 mhz c-84-dbc imd3 third-order intermodulation distortion f o1 =95mhz; f o2 =97mhz; f s =640msps; 4 interpolation c [7] -81 dbc f o1 = 153.1 mhz; f o2 = 154.1 mhz; f s =640msps; 4 interpolation i [7] -77- dbc f o1 = 137 mhz; f o2 = 143 mhz; f s =640msps; 4 interpolation c [7] -80- dbc acpr adjacent channel power ratio nco on; 4 interpolation; f s =640msps; f o = 96 mhz 1 carrier; bw = 5 mhz c - 67 - dbc 2 carriers; bw = 10 mhz c - 64 - dbc 4 carriers; bw = 20 mhz c - 60 - dbc nco on; 4 interpolation; f s = 640 msps; f o =133 mhz 1 carrier; bw = 5 mhz c - 67 - dbc 2 carriers; bw = 10 mhz c - 64 - dbc 4 carriers; bw = 20 mhz c - 59 - dbc table 5. characteristics ?continued v dda(1v8) =v ddd = 1.7 v to 1.9 v; v dda(3v3) = 3.13 v to 3.47 v; agnd and gnd are shorted together; t amb = ? 40 c to +85 c; typical values measured at v dda(1v8) =v ddd =1.8v; v dda(3v3) =3.3v; t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 11 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] delay between the deassertion of bi ts force_reset_fclk and force_reset_dclk and t he deassertion of the sync signal. it reflects the delay required by dac1008d650 to lock to a jesd 204a stream. it supposes that t he tx is already transmitting k28.5 characters in error-free conditions. [3] clkinp/clkinn inputs are at differential lvds levels. an external termination resistor with a value of between 80 and 120 (see figure 15 ) should be connected across the pins. [4] | v gpd | represents the ground potential difference voltage. this is the voltage that results from current flowing through the finite r esistance and the inductance between the receiver and the driver circuit ground voltage. [5] vin_p and vin_n inputs are differential cml input s. they are terminated internally to v tt via 50 (see figure 4 ). [6] sync_outp/sync_outn outputs are differential lvds outputs. they must be terminated by a resistor with a value of between 80 and 120 . [7] imd3 rejection with ? 6 dbfs/tone. 10. application information 10.1 general description the dac1008d650 is a dual 10-bit dac operat ing up to 650 msps. with a maximum input data rate of up to 312.5 msps and a maxi mum output sampling ra te of 650 msps, the dac1008d650 allows more flexibility for wid e bandwidth and mult i-carrier systems. combined with its quadrature modulator an d 32-bit nco, the dac1008d650 simplifies the frequency selection of the system. this is also possible because of the 2 , 4 or 8 interpolation filters which remove undesired images. dac1008d650 supports the following jesd204a key features: ? 10-bit/8-bit decoding ? code group synchronization ? inter-lane alignment ? 1+x 14 +x 15 scrambling polynomial ? character replacement ? tx/rx synchronization ma nagement via sync signals ? multiple converter devi ce alignment-multiple lanes (mcda-ml) device dac1008d650 can be interfaced with any logi c device that features high-speed serdes functionality. this macro is now widely av ailable in fpga from different vendors. standalone serdes ics can also be used. to enhance the intrinsic board layout simp lification of the jesd204a standard, nxp includes polarity swapping for each of th e lanes and additionally offers lane swapping. each physical lane can be configured logi cally as lane0, lane1, lane2 or lane3. nsd noise spectral density f s =640msps; 4 interpolation; f o = 133 mhz at 0 dbfs i- ? 145 - dbm/hz table 5. characteristics ?continued v dda(1v8) =v ddd = 1.7 v to 1.9 v; v dda(3v3) = 3.13 v to 3.47 v; agnd and gnd are shorted together; t amb = ? 40 c to +85 c; typical values measured at v dda(1v8) =v ddd =1.8v; v dda(3v3) =3.3v; t amb =+25 c; r l =50 ; i o(fs) =20ma; maximum sample rate; pll off unless otherwise specified. symbol parameter conditions test [1] min typ max unit dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 12 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a this device is mcda-ml comp liant and offers inter-lane alignment between several devices. samples alignment between devices is maintained up to output level because of an nxp proprietary mechanism. one device is configured as the master and all the others are configured as slaves. these will automatica lly align their output sa mples to the master ones. therefore, a system with several dac1008d650s can produce data with a guaranteed alignment of less than 1 dac output clock period. each dac generates two complementary current outputs on pins ioutap/ioutan and ioutbp/ioutbn. this provides a full-scale outp ut current of up to 20 ma. an internal reference is available for the reference current which is externally adjustable using pin vires. the dac1008d650 must be configured before operating. therefore, it features an spi slave interface to access internal register s. some of these registers also provide information about the jesd204a interface status. the dac1008d650 requires supplies of both 3.3 v and 1.8 v. the 1.8 v supply has separate digital and analog power supply pins. the clock input is lvds compliant. 10.2 jesd204a receiver the jedec204a defines the following parameters: l is the number of lanes per link m is the number of converters per device f is the number of bytes per frame clock period the dac1008d650 supports both lmf = 421 and lmf = 211. the current setting is configurable via the spi registers interface. the complete digital layer processing (dlp) adds a variable delay on each lane path. this is mainly because of the inter-lane alignment. [1] d = guaranteed by design. [2] frame clock cycle. the descrambler can be enabled/disabled fig 3. jesd204a receiver 10b 10b 005aaa15 7 sync_out internal configuration interface des clock align frame clock lane# 10b 10b 10b sync and word align 8b k-detect 10b/8b 8b 8b 8b 8b 8b descrambler rx controller ila (inter-lane alignment) fa (frame assembly) table 6. digital layer processing latency symbol parameter conditions test [1] min typ max unit t d delay time digital layer processing delay d 13 - 28 cycle [2] dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 13 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.2.1 lane input each lane is cml compliant. it is terminated to a common voltage with an integrated 50 resistor. the common-mode voltage is programmable by the set_vcm_voltage register as shown in table 75 on page 55 . dc coupling is only possible if both t he dac and the transmitter have the same common-mode voltage. if this is not the case ac coupling is required. the deserializer performs the incoming data clock recovery and also the serial-to-parallel conversion. therefore, each lane includes its own pll that must first lock. the clock alignment module transfers the data from the regenerated clock to the frame clock domain. the frequency of both clocks is the same but the phase relationship between the clocks is unknown. 10.2.2 sync and word align as stated in jesd204a, the transmitter and the receiver first have to synchronize. this is achieved through sync_out signals and a sync pattern (k28.5 symbol). the receiver (i.e. dac1008d650) first drives its sync_out outputs. the sync pattern is continuously sent until the receiver deasserts the sync_out signal. fig 4. lane input termination v tt 001aak16 6 50 z tt 50 vin_p vin_n fig 5. dc coupling fig 6. ac coupling 001aak16 2 50 50 50 50 z diff = 100 data in + data in ? 001aak16 3 50 50 50 50 z diff = 100 v dd1 v dd2 data in + data in ? dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 14 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a the lane processing makes use of the sync patterns to synchronize the datastream, determine the init ial running disparity and extract th e 10-bit word from the incoming datastream (word-alignment). the sync_out signal is also used during normal operation by the dac1008d650 to request a link reinitialization. this occurs wh en the 10b/8b module loses synchronization. the sync_out signal conforms to lvds signaling. its common-mode voltage and its single-ended peak amplitude can be programmed using set _sync_level bits in the set_sync registers (see table 77 on page 55 ). sync_out is asynchronous with the frame clock. there is no timing specification with respect to the clkinp and clkinn inputs. 10.2.3 comma detection and word align this stage monitors the datastream for code characters (comma detection), decodes the words to bytes (octets) and performs optional character replacement as part of frame/lane alignment monitoring and correction. this modul e provides the required control signals to the rx-controller and ila. this module decodes the 10-bit words into 8-bit words (octets). the decoding table is specified in the ieee 802.3- 2005 specification. during decoding, the disparity is calculated according to the disparity ru les mentioned in the same specification ieee 802.3-2005. when the disparity counter is more than +2 or less than ? 2, an error will be generated. the following comma symbols are detected during data transmission irrespective of the running disparity: /k/ = k28.5 /f/ = k28.7 /a/ = k28.3 /r/ = k28.0 /q/ = k28.4 a flag is sent to the control interfac e to reflect detected commas in registers. the following flags are also triggered according to the following definitions: ? valid: a code group that is found in the column of the 10b/8b decoding tables according to the current running disparity. ? disparity error: the received code group exists in the 10b/8b decoding table, but is not found in the proper column according to the current running disparity. ? not-in-table (nit) error: the received code group is not found in the 10b/8b decoding table for either disparity. ? invalid: a code group that ei ther shows a disparity error or that does not exist in the 10b/8b decoding table. dac1008d650 supports character replacement whatever the state of the descrambler. when scrambling is not active, the received k28.3 /a/ or k28. 7 /f/ will be replaced by the previous sample. when scrambling is active, the corresponding data octet d28.3 (0xc) or d28.7 (0xfc) will be used. dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 15 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.2.4 descrambler the descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x 14 +x 15 . this processing can be turned off. 10.2.5 inter-lane alignment this feature removes strict pcb design skew compensation between the lanes. 10.2.5.1 single device operation this module handles the alignment of the four data streams. because of inter-lane skew and each pll per lane concept, these alignm ent characters may be received at different times by the receivers. after the synchronization period, th e lock signal will be high. this enables the receipt of k28.3 /a/ characters. the ila_cntrl register?s sel_ila[1:0] bits select which k28.3 /a/ symbol triggers the initial lane alignment:?00? = 1st /a/ symbol, ?01? = 2nd /a/ symbol, ?10? = 3rd /a/ symbol, ?11? = 4th /a/ symbol; table 86 on page 61 . when all receivers have received their first selected /a/, they start propagating the received data to the frame assembly module at the same point in time. this module can compensate for up to 7 frame clock period misalignments between the lanes. when initial lane alignment is not supported, the manual alignment mode can be used. after the initial ila sequence, the lane alignment monitoring starts. if the received user data contains a k28.3 /a/ symbol: ? its position is compared to the value of the alignment monitor counter ? if two successive k28.3 /a/ symbols have been received at a wrong position, a realignment takes place ? if the buffers are empty or overflow, this is indicated by the registers ila_buf_err_ln0 to ila_buf_err_ln3 10.2.5.2 multi-device operation dac1008d650 implements a multi-device inter-lane alignment that guarantees a skew of less than one output period between them. two modes are available: master/slave and all slave. both make use of the mds_p and mds_n pins. dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 16 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a each dac device of the system gener ates its own reference (ref_a in figure 7 ). if configured as a slave, an early-late compar ator compares the internal reference with the external reference provided by the mds pins. the comparator controls an internal buffer that is used to delay the samples. fig 7. multi-device synchronization (mds) implementation 001aal07 3 i buffer q dig lanes comp mds_a ref_a sync~ mds_a_out mds_a ck dac clk mgmt dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 17 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.2.5.3 master/slave mode the external reference is provided by one of the dacs (the master dac), which has to be configured to do this. the others are set to slave mode. fig 8. master-slave mode 001aal07 0 ref_a sync_0 mds_out mds_in i buffer q dig comp ref_a sync_1 mds_out mds_in dac clk mgmt i buffer master dac 0 slave dac 1 slave dac 2 q dig tx comp ref_a sync_2 mds_out mds_in dac clk mgmt clock distribution ref_clock q i buffer dig comp dac clk mgmt dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 18 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a the mds signal generated by the master da c must reach all slaves within one dac output clock period. this induces pcb layout constraints for the mds signal and also for the clock distribution. because trace lengths di ffer, the clock edges will reach each of the dacs at different times. the worst case clock skew is given by t 1 =ph01 ? ph03, where ph0x represents the sum of the trace delay and the clock skew at the output of the clock generator. the maximum allowable trace delay for the mds signal is given by t=tdac ? t 1 . fig 9. clock skew case 1: master is the farthest 001aal0 72 ref clock tdac master clock ph03 slave 1 clock ph02 slave 2 clock ph01 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 19 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a the worst case clock skew is given by t 2 =ph03 ? ph01. the minimum allowable trace delay for the mds signal is given by t= t 2 . in real applications, the master dac can be anywhere and both conditions must be satisfied: t 2 < t mds dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 22 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a fig 12. frame assembly 005aaa15 3 dac0 serial clock 3.125 ghz encoded octet b9 b0 lane 0 b1 b2 b3 b4 b5 b6 b7 b8 b9 deserializer b8 b7 b6 b5 b4 b3 b2 b1 b0 character clock 312.5 mhz scrambled octet s7 10b/8b s6 s5 s4 s3 s2 s1 s0 frame clock 312.5 mhz byte 0 /f d09 on/off /10 descrambler d08 d07 d06 d05 d04 d03 d02 encoded octet b9 b0 lane 1 b1 b2 b3 b4 b5 b6 b7 b8 b9 deserializer b8 b7 b6 b5 b4 b3 b2 b1 b0 scrambled octet s7 10b/8b s6 s5 s4 s3 s2 s1 s0 byte 1 d01 on/off /10 descrambler frame assembly d00 t t t t t t byte 2 f = 1 byte m = 2 converters d09 d08 d07 d06 d05 d04 d03 d02 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 byte 3 d01 d00 t t t t t t encoded octet b9 b0 lane 2 b1 b2 b3 b4 b5 b6 b7 b8 b9 deserializer b8 b7 b6 b5 b4 b3 b2 b1 b0 scrambled octet s7 10b/8b s6 s5 s4 s3 s2 s1 s0 on/off /10 descrambler encoded octet b9 b0 lane 3 b1 b2 b3 b4 b5 b6 b7 b8 b9 deserializer b8 b7 b6 b5 b4 b3 b2 b1 b0 scrambled octet s7 10b/8b s6 s5 s4 s3 s2 s1 s0 on/off /10 descrambler dac1 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 23 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.3 serial periphera l interface (spi) 10.3.1 protocol description the dac1008d650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. it provides access to the registers that define the operating modes of the chip in both write mode and read mode. this interface can be configured as a 3-wire ty pe (sdio as bidirectional pin) or a 4-wire type (sdio and sdo as unidirectional pin, in put and output port respectively). in both configurations, sclk acts as the serial clo ck and scs_n acts as the serial chip select bar. each read/write operation is sequenced by the scs_n signal and enabled by a low assertion to drive the chip with two bytes to five bytes, depending on the content of the instruction byte (see ta b l e 8 ). in table 8 below, n1 and n0 indicate the number of bytes transferred after the instruction byte. a[4:0] indicates which register is being addressed. in the case of a multiple transfer, this address points to the first register to be accessed. the address is then internally decreased after each following data phase. r/w indicates the mode access, (see table 7 ). fig 13. spi protocol 001aaj81 2 reset_n scs_n sclk sdio sdo (optional) r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 7. read or write mode access description r/w description 0 write mode operation 1 read mode operation table 8. number of bytes to be transferred n1 n0 number of bytes transferred 001 012 103 114 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 24 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.3.2 spi timing description the spi interface can operate at a frequency of up to 15 mhz. the spi timing is shown in figure 14 . the spi timing characteristics are given in ta b l e 9 . fig 14. spi timing diagram table 9. spi timing characteristics symbol parameter min typ max unit f sclk sclk frequency - - 15 mhz t w(sclk) sclk pulse width 30 - - ns t su(scs_n) scs_n set-up time 20 - - ns t h(scs_n) scs_n hold time 20 - - ns t su(sdio) sdio set-up time 10 - - ns t h(sdio) sdio hold time 5 - - ns t w(reset_n) reset_n pulse width 30 - - ns 001aaj81 3 50 % t w(reset_n) t su(scs_n) t su(sdio) t h(sdio) t h(scs_n) t w(sclk) 50 % reset_n scs_n sclk sdio 50 % 50 % dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 25 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.4 clock input the dac1008d650 has one differential clock input, clkinn/clkinp. the dac1008d650 can operate with a clock frequency up to 312.5 mhz or up to 650 mhz if the internal pll is bypassed. the clock input can be lvds (see figure 15 ) but it can also be interfaced with cml (see figure 16 ). error free data transition from one internal clock domain to another one is handled by clock domain in terface (cdi) logic. during the reset phase (reset_n asserted), the cl ock must be stable and running. this ensures a proper reset of the complete device. the device has no embedded po wer-on-reset feature. drivi ng the reset_n pin to set the device to its default state is mandatory. fig 15. lvds clock configuration fig 16. interfacing cml to lvds 001aah02 1 100 lvds clkinp clkinn lvds z diff = 100 001aah02 0 55 55 1.1 k 2.2 k 100 nf cml 100 nf 100 nf clkinp lvds clkinn agnd v dda(1v8) 1 k z diff = 100 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 26 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.5 fir filters the three interpolation fir filters have a st op band attenuation of at least 80 dbc and a pass band ripple of less than 0,0005 db. table 10. interpolation filter coefficients first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value h(1) h(55) ? 4 h(1) h(23) ? 2 h(1) h(15) ? 39 h(2) h(54) 0 h(2) h(22) 0 h(2) h(14) 0 h(3) h(53) 13 h(3) h(21) 17 h(3) h(13) 273 h(4) h(52) 0 h(4) h(20) 0 h(4) h(12) 0 h(5) h(51) ? 34 h(5) h(19) ? 75 h(5) h(11) ? 1102 h(6) h(50) 0 h(6) h(18) 0 h(6) h(10) 0 h(7) h(49) 72 h(7) h(17) 238 h(7) h(9) 4964 h(8) h(48) 0 h(8) h(16) 0 h(8) - 8192 h(9) h(47) ? 138 h(9) h(15) ? 660 - - - h(10) h(46) 0 h(10) h(14) 0 - - - h(11) h(45) 245 h(11) h(13) 2530 - - - h(12) h(44) 0 h(12) - 4096 - - - h(13) h(43) ? 408------ h(14)h(42)0------ h(15) h(41) 650 - - - - - - h(16)h(40)0------ h(17) h(39) ? 1003------ h(18)h(38)0------ h(19) h(37) 1521 - - - - - - h(20)h(36)0------ h(21) h(35) ? 2315------ h(22)h(34)0------ h(23) h(33) 3671 - - - - - - h(24)h(32)0------ h(25) h(31) ? 6642------ h(26)h(30)0------ h(27) h(29) 20756 - - - - - - h(28)-32768------ dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 27 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.6 quadrature modulator and numerica lly controlled oscillator (nco) the quadrature modulator allows the 10-bit i and q data to be mixed with the carrier signal generated by the nco. the frequency of the nco is programmed over 32 bits and the sign of the sine component can be inverted in order to operate positive or negative, lower or upper single sideband up-conversion. 10.6.1 nco in 32-bit when using the nco, the frequency can be set by the four registers freqnco_lsb, freqnco_lisb, freqnco_uisb a nd freqnco_msb over 32 bits. the frequency for the nco in 32-bit is calculated as follows: (1) where m is the decimal representation of freq_nco[31:0]. the phase of the nco can be set from 0 to 360 by both registers phinco_lsb and phinco_msb over 16 bits. the default setting is f nco = 96 mhz when f s = 640 msps and the default phase is 0 . 10.6.2 low-power nco when using the low-power nco, the frequency can be set by the five msbs of register freqnco_msb. the frequency for the low-power nco is calculated as follows: (2) where m is the decimal representation of freq_nco[31:27]. the phase of the low-power nco can be se t by the five msbs of the register phinco_msb. 10.6.3 minus_3db during normal use, a full-scale pattern will al so be full-scale at the output of the dac. nevertheless, when the i and q data are simult aneously close to full-scale, some clipping can occur and the minus_3db function can be used to reduce the gain in the modulator by 3 db. this is to keep a full-sca le range at the output of the dac without added interferers. 10.7 x / (sin x) the roll-off effect of the dac causes a selectab le fir filter to be in serted to compensate for the (sin x) / x effect. this filter intro duces a dc loss of 3.4 db. the coefficients are represented in ta b l e 11 . f nco mf s 2 32 -------------- = f nco mf s 2 5 -------------- = dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 28 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.8 dac transfer function the full-scale output current for each dac is the sum of the two complementary current outputs: (3) the output current depends on the digital input data: (4) (5) the setting applied to register common bit df (register 00h[2]; see table 17 ? page 0 register allocation map ? ) defines whether the dac1008d65 0 operates with a binary input or a two?s complement input. ta b l e 1 2 shows the output current as a fu nction of the input data, when i o(fs) =20ma. table 11. inversion filter coefficients first interpolation filter lower upper value h(1) h(9) 2 h(2) h(8) ? 4 h(3) h(7) 10 h(4) h(6) ? 35 h(5) - 401 table 12. dac transfer function data i9/q9 to i0/q0 ioutnp ioutnn binary two?s complement 0 00 0000 0000 10 0000 0000 0 ma 20 ma ... ... ... ... ... 2048 10 0000 00 00 00 0000 0000 10 ma 10 ma ... ... ... ... ... 4095 11 1111 1111 01 1111 1111 20 ma 0 ma i ofs () i ioutp i ioutn + = i ioutp i ofs () data 1023 --------------- - ?? ?? = i ioutn i ofs () 1023 data ? 1023 --------------------------------- - ?? ?? = dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 29 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.9 full-scale current 10.9.1 regulation the dac1008d650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 v reference to the gapout pin. it is recommended to decouple pin gapout using a 100 nf capacitor. the reference current is generated via an external resistor of 909 (1 %) connected to pin vires. a control amplifier sets the appropriate full-scale current (i o(fs) ) for both dacs (see figure 17 ). this configuration is optimum for temper ature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. 10.9.1.1 external regulation the dac current can also be set by applying an external reference voltage to the non-inverting input pin gapout and disabling the internal bandgap reference voltage with bit gap_pd (register 00h[0]; see table 18 ? common register (address 00h) bit description ? ). 10.9.2 full-scale current adjustment the default full-scale current (i o(fs) ) is 20 ma but further adjustments can be made by the user to both dacs independently using the serial interface from 1.6 ma to 22 ma, 10 %. the settings applied to dac_a_gain _coarse[3:0] (register 0ah; see table 28 ? dac_a_cfg_2 register (address 0ah) bit description ? and register 0bh; see table 29 ? dac_a_cfg_3 register (address 0bh) bit description ? ) and dac_b_gain coarse[3:0] (register 0dh; see table 31 ? dac_b_cfg_2 register (address 0dh) bit description ? and register 0eh; see table 32 ? dac_b_cfg_3 register (address 0eh) bit description ? ) define the coarse variation of the full-scale current (see ta b l e 1 3 ). fig 17. internal reference configuration 001aaj81 6 ref. bandgap gapout vires dac current sources array agnd agnd 100 nf 909 (1 %) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 30 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a the settings applied to dac_a_ga in_fine[5:0] (register 0ah; see table 28 ? dac_a_cfg_2 register (address 0ah) bit description ? ) and to dac_b_gain_fine[5:0] (register 0dh; see table 31 ? dac_b_cfg_2 register (address 0dh) bit description ? ) define the fine variation of the full-scale current (see table 14 ). the coding of the fine gain adjustment is two?s complement. 10.10 digital offset correction when the dac1008d650 analog output is dc connected to the next stage, the digital offset correction can be used to adjust the co mmon-mode level at the output of the dac. it adds an offset at the end of the digital part, just before the dac. the settings applied to dac_a_offset[11:0] (register 09h; see table 27 ? dac_a_cfg_1 register (address 09h) bit description ? and register 0bh; see table 29 ? dac_a_cfg_3 register (address 0bh) bit description ? ) and to ?dac_b_offset[11:0]? table 13. i o(fs) coarse adjustment default settings are shown highlighted. dac_gain_coarse[3:0] i o(fs) (ma) decimal binary 0 0000 1.6 1 0001 3.0 2 0010 4.4 3 0011 5.8 4 0100 7.2 5 0101 8.6 6011010.0 7011111.4 8 1000 12.8 9 1001 14.2 10 1010 15.6 11 1011 17.0 12 1100 18.5 13 1101 20.0 14 1110 21.0 15 1111 22.0 table 14. i o(fs) fine adjustment default settings are shown highlighted. dac_gain_fine[5:0] delta i o(fs) decimal two?s complement ? 32 10 0000 ? 10 % ... ... ... 0 00 0000 0 ... ... ... 31 01 1111 +10 % dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 31 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a (register 0ch; see table 30 ? dac_b_cfg_1 register (address 0ch) bit description ? and register 0eh; see table 32 ? dac_b_cfg_3 register (address 0eh) bit description ? ) define the range of variation of the digital offset (see ta b l e 1 5 ). 10.11 analog output the dac1008d650 has two output channels each of which produces two complementary current outputs. these allow the even-order harmonics and noise to be reduced. the pins are ioutap/ioutan and ioutbp/ioutbn respectively and need to be connected via a load resistor r l to the 3.3 v analog power supply (v dda(3v3) ). the equivalent analog output circuit of one dac is shown in figure 18 . this circuit consists of a parallel combination of nmos current sources, and their associated switches, for each segment. the cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of t he dac by introducing less distortion. the device can provide an output level (v o(p-p) ) of up to 2 v, depending on the application, the following stages and the targeted performances. table 15. digital offset adjustment default settings are shown highlighted. dac_offset[11:0] offset applied decimal two?s complement ? 2048 1000 0000 0000 ? 4096 ? 2047 1000 0000 0001 ? 4094 ... ... ... ? 1 1111 1111 1111 ? 2 0 0000 0000 0000 0 +1 0000 0000 0001 +2 ... ... ... 2046 0111 1111 1110 +4092 2047 0111 1111 1111 +4094 fig 18. equivalen t analog output circuit (one dac) 001aah01 9 v dda(3v3) agnd ioutap/ioutbp ioutan/ioutbn r l r l agnd dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 32 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.12 auxiliary dacs the dac1008d650 in tegrates two auxiliary dacs that can be used to compensate for any offset between the dac and the next stage in the transmission path. both auxiliary dacs have a 10-bit resolution and are curr ent sources (r eferenced to ground). (6) the output cu rrent depends on the auxiliary dac data: (7) (8) ta b l e 1 6 shows the output curr ent as a function of the auxiliary dac data. table 16. auxiliary dac transfer function default settings are shown highlighted. data aux[9:0] (binary) i auxp i auxn 0 00 0000 0000 0 ma 2.2 ma ... ... ... ... 512 10 0000 0000 1.1 ma 1.1 ma ... ... ... ... 1023 11 1111 1111 2.2 ma 0 ma i oaux () i auxp i auxn + = auxp i oaux () aux 9:0 [] 1023 ------------------------ - ?? ?? = auxn i oaux () (1023 a ? ux 9:0 []) 1023 --------------------------------------------- ?? ?? = dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 33 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.13 output c onfiguration 10.13.1 basic output configuration the use of a differentially-coupled transf ormer output provides optimum distortion performance (see figure 19 ). in addition, it helps to match the impedance and provides electrical isolation. the dac1008d650 can operate at a v o(p-p) of 2 v differential outputs. in this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 v analog power supply, in order to adjust the dc common-mode to approximately 2.7 v (see figure 20 ). fig 19. 1 v o(p-p) differential output with transformer fig 20. 2 v o(p-p) differential output with transformer 001aaj81 7 50 50 50 ioutnp/ioutnn; v o(cm) = 2.8 v; v o(dif)(p-p) = 1 v ioutnp ioutnn 0 ma to 20 ma 2:1 0 ma to 20 ma v dda(3v3) v dda(3v3) 001aaj81 8 50 100 100 ioutnp/ioutnn; v o(cm) = 2.7 v; v o(dif)(p-p) = 2 v ioutnp ioutnn 0 ma to 20 ma 4:1 0 ma to 20 ma v dda(3v3) 62 v dda(3v3) v dda(3v3) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 34 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.13.2 dc interface to an analog quadrature modulator (aqm) when the system operation requires to keep the dc component of the spectrum, the dac1008d650 must use a dc interface to connect to an aqm. in this case, the offset compensation for lo cancellation can be made with the use of the digital offset control in the dac. figure 21 is an example of a connection to an aqm with a common-mode input level (v i(cm) ) of 1.7 v. figure 22 is an example of a connection to an aqm with a common-mode input level (v i(cm) ) of 3.3 v. the auxiliary dacs can be used to control the offset in a pr ecise range or with precise steps. fig 21. example of a dc interface co nnection to an aqm with a v i(cm) of 1.7 v fig 22. example of a dc interface co nnection to an aqm with a v i(cm) of 3.3 v 001aaj54 1 51.1 51.1 442 442 v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp (1) ioutnp/ioutnn; v o(cm) = 2.67 v; v o(dif)(p-p) = 1.98 v (2) bbp/bbn; v i(cm) = 1.7 v; v i(dif)(p-p) = 1.26 v bbn aqm (v i(cm) = 1.7 v) 768 768 (1) (2) 001aaj54 2 54.9 54.9 237 237 v dda(3v3) ioutnp ioutnn bbp bbn aqm (v i(cm) = 3.3 v) 750 750 5 v 1.27 k 1.27 k (1) ioutnp/ioutnn; v o(cm) = 2.75 v; v o(dif)(p-p) = 1.97 v (2) bbp/bbn; v i(cm) = 3.3 v; v i(dif)(p-p) = 1.5 v (1) (2) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 35 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a figure 23 is an example of a dc interface con nected to an aqm with a common-mode input level (v i(cm) ) of 1.7 v when using auxiliary dacs. figure 24 is an example of a dc interface co nnected to an to an aqm with a common-mode input level (v i(cm) ) of 3.3 v when using auxiliary dacs. the constraints to adjusting the interface are the output compliance range of the dac and the auxiliary dacs, the input common-mode leve l of the aqm, and t he range of offset correction. fig 23. example of a dc interface co nnection to an aqm with a v i(cm) of 1.7 v when using auxiliary dacs fig 24. example of a dc interface co nnection to an aqm with a v i(cm) of 3.3 v when using auxiliary dacs 001aaj54 3 51.1 51.1 442 442 v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp bbn aqm (v i(cm) = 1.7 v) 698 698 51.1 51.1 auxnp auxnn 1.1 ma (typ.) (1) ioutnp/ioutnn; v o(cm) = 2.67 v; v o(dif)(p-p) = 1.94 v (2) bbp/bbn; v i(cm) = 1.7 v; v i(dif)(p-p) = 1.23 v; offset correction up to 36 mv (1) (2) 001aaj54 4 54.9 54.9 237 237 3.3 v ioutnp ioutnn auxnp auxnn bbp bbn aqm (v i(cm) = 3.3 v) 750 750 5 v 634 634 442 442 (1) ioutnp/ioutnn; v o(cm) = 2.75 v; v o(dif)(p-p) = 1.96 v (2) bbp/bbn; v i(cm) = 3.3 v; v i(dif)(p-p) = 1.5 v; offset correction up to 36 mv (1) (2) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 36 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.13.3 ac interface to an analog quadrature modulator (aqm) when the aqm common-mode voltage is close to ground, the dac1008d650 must be ac-coupled and the auxiliary dacs are needed for offset correction. figure 25 is an example of a connection to an aqm with a common-mode input level (v i(cm) ) of 0.5 v when using auxiliary dacs. fig 25. example of a dc interface co nnection to an aqm with a v i(cm) of 0.5 v when using auxiliary dacs 001aaj589 66.5 66.5 10 nf v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp bbn aqm (v i(cm) = 0.5 v) 2 k 2 k 5 v 174 174 34 34 auxnp auxnn 1.1 ma (typ.) 10 nf (1) ioutnp/ioutnn; v o(cm) = 2.65 v; v o(dif)(p-p) = 1.96 v (2) bbp/bbn; v i(cm) = 0.5 v; v i(dif)(p-p) = 1.96 v; offset correction up to 70 mv (1) (2) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 37 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.13.4 phase correction the analog quadrature modulator which follo ws the dacs may have a phase imbalance which will result in undesired sidebands. by adjusting the phase between the i and q channels, the spur can be reduced. without compensation the i and q have a phase difference of /2 (90 ). the registers phasecorr_cntrl0 and phasecorr_cntrl1 lo cated in register page 0 allow a phase variation from 75.7 to 104.3 . the two registers define a signed value that ranges from ? 512 to +511. the resulting phase compensa tion (in radians) is given by the equation: phase_corr[9:0] / 2048. 10.14 power and grounding the power supplies should be decoupled with th e following ground pins to optimize the decoupling: ? v dda(1v8) : pin 38 with pin 37; pin 44 with pin 43; pin 11 with pin 12; pin 17 with pin 18; pin 32 with pin 31 10.15 configuration interface 10.15.1 register description dac1008d650 implements indirect addressing using a page access method. the page-address is located at address 0x1f and is by default 0x00, which selects page 0 as default page. for example, to access regi sters which configure the jesdrx, one must first activate page 4 by writing 0x04 to the page-address 0x1f. the dac1008d650 contains six different pages. the device has no embedded po wer-on-reset feature. drivi ng the reset_n pin to set the device to its default state is mandatory. 10.15.2 detailed descriptions of registers the register information has been provided in page form accompanied by a detailed description for each bit in the tables following the register allocation map of each page. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 38 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.1 page 0 allocation map description table 17. page 0 register allocation map address register name r/w bit definition default b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h common r/w spi_3w spi_rst - - - df pd_all pd_gap 10000100 84h 1 01h txcfg r/w nco_en nco_lp_sel inv_sine _en mode[2:0] int_fir[1:0] 00000001 01h 2 02h pllcfg r/w pll_pd - - pll_div[1:0] pll_phase[1:0] pll_pol 00000000 00h 3 03h freqnco_lsb r/w freq_nco[7:0] 01100110 66h 4 04h freqnco_lisb r/w freq_nco[15:8] 01100110 66h 5 05h freqnco_uisb r/w freq _nco[23:16] 01100110 66h 6 06h freqnco_msb r/w fre q_nco[31:24] 00100110 26h 7 07h phinco_lsb r/w ph_nco[7:0] 00000000 00h 8 08h phinco_msb r/w ph_nco[15:8] 00000000 00h 9 09h dac_a_cfg_1 r/w dac_a_pd dac_a_sleep dac_a_offset[5:0] 00000000 00h 10 0ah dac_a_cfg_2 r/w dac_a_gain_coar se[1:0] dac_a_gain_fine[5:0] 01000000 40h 11 0bh dac_a_cfg_3 r/w dac_a_gain_coar se[3:2] dac_a_offset[11:6] 11000000 c0h 12 0ch dac_b_cfg_1 r/w dac_b_pd dac_b_sleep dac_b_offset[5:0] 00000000 00h 13 0dh dac_b_cfg_2 r/w dac_b_gain_coar se[1:0] dac_b_gain_fine[5:0] 01000000 40h 14 0eh dac_b_cfg_3 r/w dac_b_gain_coar se[3:2] dac_b_offset[11:6] 11000000 c0h 15 0fh dac_cfg r/w - - - - - - minus_ 3db noise_ shaper 00000000 00h 17 11h dac_current_0 r/w - - - - dac_dig_bias[2:0] - 00000110 06h 18 12h dac_current_1 r/w - dac_mst_bias[2:0] - 00000110 06h 19 13h dac_current_2 r/w dac_drv_bias[2:0] - dac_slv_bias[2:0] - 01100110 66h 20 14h dac_current_3 r/w dac_ck_bias[2: 0] - dac_cas_bias[2:0] - 01100110 66h 21 15h dac_sel_ph_ fine r/w - - - - - - sel_ph_fine[1:0] 00000010 02h 22 16h phasecorr_ cntrl0 r/w phase_corr[7:0] 00000000 00h 23 17h phasecorr_ cntrl1 r/w phase_corr_ enable - - - - - phase_corr[9:8] 00000000 00h 26 1ah dac_a_aux_msb r/w aux_a[9:2] 10000000 80h 27 1bh dac_a_aux_lsb r/w aux_a_pd - - - - - aux_a[1:0] 00000000 00h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 39 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 28 1ch dac_b_aux_msb r/w aux_b[9:2] 10000000 80h 29 1dh dac_b_aux_lsb r/w aux_b_pd - - - - - aux_b[1:0] 00000000 00h 31 1fh page_address r/w - - - - - page[2:0] 00000000 00h table 17. page 0 register allocation map ?continued address register name r/w bit definition default b7 b6 b5 b4 b3 b2 b1 b0 bin hex dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 40 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.2 page 0 bit definition detailed description please refer to ta b l e 1 7 for a register overview for page 0. in the following tables, all the values emphasized in bold are the default values. table 18. common register (address 00h) bit description default settings are shown highlighted. bit symbol access value description 7 spi_3w r/w serial interface bus type 0 4 wire spi 1 3 wire spi 6 spi_rst r/w serial interface reset 0 no reset 1 performs a reset on all registers except 0x00 2 df r/w data format 0 signed (two?s compliment) format 1 unsigned format 1 pd_all r/w power-down 0 no action 1 all circuits (digital and analog) are switched off 0 gap_pd r/w internal bandgap power-down 0 no action 1 internal bandgap references are switched off table 19. txcfg register (address 01h) bit description default settings are shown highlighted. bit symbol access value description 7 nco_en r/w nco 0 disabled (the nco phase is reset to 0) 1 enabled 6 nco_lp_sel r/w low-power nco 0 nco may use all 32 bits 1 nco frequency and phase given by the five msbs of the registers 06h and 08h respectively 5 inv_sine_en r/w x / (sin x) function 0 disabled 1 enabled 4 to 2 mode[2:0] r/w modulation 000 dual dac: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion 011 negative upper single sideband up-conversion 100 negative lower single sideband up-conversion dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 41 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 1 to 0 int_fir[1:0 ] r/w interpolation 00 no interpolation 01 2 10 4 11 8 table 19. txcfg register (address 01h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 20. pllcfg register (a ddress 02h) bit description default settings are shown highlighted. bit symbol access value description 7 pll_pd r/w pll 0 switched on 1 switched off 6 - r/w 0 undefined 5 - r/w 0 must be written with ?0? 4 to 3 pll_div[1:0] r/w pll divider factor 00 2 01 4 10 8 2 to 1 pll_phase[1:0] r/w pll phase shift of f s 00 0 01 120 10 240 11 undefined 0 pll_pol r/w clock edge of dac (f s ) 0 normal 1 inverted table 21. freqnco_lsb register (address 03h) bit description bit symbol access value description 7 to 0 freq_nco[7:0] r/w 66h lower 8 bits for the nco frequency setting table 22. freqnco_lisb register (address 04h) bit description bit symbol access value description 7 to 0 freq_nco[15:8] r/w 66h lower intermediate 8 bits for the nco frequency setting table 23. freqnco_uisb register (address 05h) bit description bit symbol access value description 7 to 0 freq_nco[23:16] r/w 66h upper intermediate 8 bits for the nco frequency setting dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 42 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 24. freqnco_msb register (address 06h) bit description bit symbol access value description 7 to 0 freq_nco[31:24] r/w 26h most signific ant 8 bits for the nco frequency setting table 25. phinco_lsb register (address 07h) bit description bit symbol access value description 7 to 0 ph_nco[7:0] r/w 00h lower 8 bits for the nco phase setting table 26. phinco_msb register (address 08h) bit description bit symbol access value description 7 to 0 ph_nco[15:8] r/w 00h most significant 8 bits for the nco phase setting table 27. dac_a_cfg_1 register (address 09h) bit description default settings are shown highlighted. bit symbol access value description 7 dac_a_pd r/w dac a power 0on 1off 6 dac_a_sleep r/w dac a sleep mode 0 disabled 1 enabled 5 to 0 dac_a_offset[5:0] r/w 00h lower 6 bits for the dac a offset table 28. dac_a_cfg_2 register (address 0ah) bit description bit symbol access value description 7 to 6 dac_a_gain_coarse[1:0] r/w 1h least significant 2 bits for the dac a gain setting for coarse adjustment 5 to 0 dac_a_gain_fine[5:0] r/w 00h the 6 bits for the dac a gain setting for fine adjustment table 29. dac_a_cfg_3 register (address 0bh) bit description bit symbol access value description 7 to 6 dac_a_gain_coarse[3:2] r/w 3h most significant 2 bits for the dac a gain setting for coarse adjustment 5 to 0 dac_a_offset[11:6] r/w 00h most significant 6 bits for the dac a offset dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 43 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 30. dac_b_cfg_1 register (address 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 dac_b_pd r/w dac b power 0on 1off 6 dac_b_sleep r/w dac b sleep mode 0 disabled 1 enabled 5 to 0 dac_b_offset[5:0] r/w 00h lower 6 bits for the dac b offset table 31. dac_b_cfg_2 register (address 0dh) bit description bit symbol access value description 7 to 6 dac_b_gain_coarse[1:0] r/w 1h least significant 2 bits for the dac b gain setting for coarse adjustment 5 to 0 dac_b_gain_fine[5:0] r/w 00h the 6 bits for the dac b gain setting for fine adjustment table 32. dac_b_cfg_3 register (address 0eh) bit description bit symbol access value description 7 to 6 dac_b_gain_coarse[3:2] r/w 3h most significant 2 bits for the dac b gain setting for coarse adjustment 5 to 0 dac_b_offset[11:6] r/w 00h most significant 6 bits for the dac b offset table 33. dac_cfg register (address 0fh) bit description default settings are shown highlighted. bit symbol access value description 1 minus_3db r/w nco gain 0unity 1 ? 3 db 0 noise_shaper r/w noise shaper 0 disabled 1 enabled table 34. dac_current_0 register (address 11h) bit description default settings are shown highlighted. bit symbol access value description 3 to 1 dac_dig_bias[2:0] r/w 3h bias current control (see ta b l e 4 6 ) table 35. dac_current_1 register (address 12h) bit description default settings are shown highlighted. bit symbol access value description 3 to 1 dac_mst_bias[2:0] r/w 3h bias current control (see ta b l e 4 6 ) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 44 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 36. dac_current_2 register (address 13h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 dac_drv_bias[2:0] r/w 3h bias current control (see ta b l e 4 6 ) 3 to 1 dac_slv_bias[2:0] r/w 3h bias current control (see ta b l e 4 6 ) table 37. dac_current_3 register (address 14h) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 dac_ck_bias[2:0] r/w 3h bias current control (see ta b l e 4 6 ) 3 to 1 dac_cas_bias[2:0] r/w 3h bias current control (see ta b l e 4 6 ) table 38. dac_sel_ph_fine register (address 15h) bit description default settings are shown highlighted. bit symbol access value description 1 to 0 sel_ph_fine[1:0] r/w 2h fine dac phase selection table 39. phasecorr_cntrl0 register (address 16h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 phase_corr[7:0] r/w 00h lsb phase correction factor table 40. phasecorr_cntrl1 register (address 17h) bit description default settings are shown highlighted. bit symbol access value description 7 phase_corr_enable r/w phase correction 0 disabled 1 enabled 1 to 0 phase_corr[9:8] r/w 0h m sb phase correction factor table 41. dac_a_aux_msb register (address 1ah) bit description bit symbol access value description 7 to 0 aux_a[9:2] r/w 80h most significant 8 bits for auxiliary dac a table 42. dac_a_aux_lsb register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 aux_a_pd r/w auxiliary dac a power 0on 1off 1 to 0 aux_a[1:0] r/w 0h lower 2 bits for auxiliary dac a table 43. dac_b_aux_msb register (address 1ch) bit description bit symbol access value description 7 to 0 aux_b[9:2] r/w 80h most significant 8 bits for auxiliary dac b dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 45 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 44. dac_b_aux_lsb register (address 1dh) bit description default settings are shown highlighted. bit symbol access value description 7 aux_b_pd r/w auxiliary dac b power 0on 1off 1 to 0 aux_b[1:0] r/w 0h lower 2 bits for auxiliary dac b table 45. dac_b_aux_lsb register (address 1dh) bit description default settings are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w 0h page address table 46. bias current control table default settings are shown highlighted. bias[2:0] deviation from nominal current 000 ? 30 % 001 ... 010 ... 011 0 % 100 ... 101 ... 110 ... 111 +30 % xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 46 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.3 page 1 allocation map description [1] u = undefined at power-up or after reset. table 47. page 1 register allocation map address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h mds_main r/w mds_eqcheck[1:0] mds_ run mds_nco mds_sel_ ln23 mds_32t_ ena mds_ master mds_ ena 00000100 04h 1 01h mds_win_period_a r/w mds_win_period_a[7:0] 10000000 80h 2 02h mds_win_period_b r/w mds_win_period_b[7:0] 01000000 40h 3 03h mds_misccntrl0 r/w - - - mds_eval_ ena mds_ prerun_ ena mds_pulsewidth[2:0] 00010000 10h 4 04h mds_man_adjustd ly r/w mds_ man mds_man_adjustdly[6:0] 01000000 40h 5 05h mds_auto_cycles r/w mds_auto_cycles[7:0] 10000000 80h 6 06h mds_misccntrl1 r/w mds_sr_ cken mds_sr_ lockout mds_ sr_ lock mds_ relock mds_lock_delay[3:0] 00001111 0fh 8 08h mds_adjdelay r - mds_adjdelay[6:0] uuuuuuuu uuh 9 09h mds_status0 r early late equal mds_lock early_ error late_ error equal_ found mds_ active uuuuuuuu uuh 10 0ah mds_status1 r - - - - jd_odd mds_ prerun mds_ lockout mds_ lock uuuuuuuu uuh 31 1fh page_address r/w - - - - - page[2:0] 00000000 00h dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 47 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.4 page 1 bit definition detailed description please refer to ta b l e 4 7 for a register overview and their default values. in the following tables, all the values emphasized in bold are the default values. table 48. mds_main register (address 00h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 mds_eqcheck[1:0] r/w lock mode 00 lock when (early = 1 and late = 1) 01 lock when (early = 1 and late = 1 and equal = 1) 10 lock when equal = 1 11 force_lock (equal-check = 1) 5 mds_run r/w evaluation restart 0 no action 1 transition from 0 to 1 restarts evaluation_counter 4 mds_nco r/w nco synchronization 0 no action 1 nco synchronization enabled 3 mds_sel_ln23 r/w synchronization reference 0 use lane 1 enable as reference for synchronization 1 use lane 2/lane 3 enable as reference for synchronization 2 mds_32t_ena r/w maximum delay 0 maximum coarse delay is 16t_dclk 1 maximum coarse delay is 32t_dclk 1 mds_master r/w mds mode 0 slave mode 1 master mode 0 mds_ena r/w mds function 0 disable mds function 1 enable mds function table 49. mds_win_period_a register (address 01h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 mds_win_period_a[7:0] r/w 80h determines mds window low-time table 50. mds_win_period_b register (address 02h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 mds_win_period_b[7:0] r/w 40h determines mds window high-time dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 48 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 51. mds_misccntrl0 register (address 03h) bit description default settings are shown highlighted. bit symbol access value description 4 mds_eval_ena r/w mds evaluation 0 disabled 1 enabled 3 mds_prerun_ena r/w automatic mds start-up 0 no mds_win/mds_ref generation in advance 1 mds_win/mds_ref run-in before mds evaluation 2 to 0 mds_pulsewidth[2:0] r/w width of mds (in output clk-periods) 000 1t 001 2t 010 to 111 (mds_pulsewidth ? 1) 4t table 52. mds_man_adjustdly register (address 04h) bit description default settings are shown highlighted. bit symbol access value description 7 mds_man r/w adjustment delay mode 0 auto-control adjustment delays 1 manual control adjustment delays 6 to 0 mds_man_adjustdly[6:0] r/w adjustment delay value 40h if mds_man = 0 then initial value adjustment delay - if mds_man = 1 then controls adjustment delay table 53. mds_auto_cycles register (address 05h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 mds_auto_cycles[7:0] r/w 80h numbe r of evaluation cycles applied for mds table 54. mds_misccntrl1 register (address 06h) bit description default settings are shown highlighted. bit symbol access value description 7 mds_sr_cken r/w lock mode 0 free-running mds_cken 1 mds_cken forced low 6 mds_sr_lockout r/w lockout detector soft reset 0 mds_sr_lockout in use 1 mds_sr_lockout forced low 5 mds_sr_lock r/w lock detector soft reset 0 mds_sr_lock in use 1 mds_sr_lock forced low dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 49 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 4 mds_relock r/w relock mode 0 no action 1 relock when lockout occurs 3 to 0 mds_lock_delay[3:0] r/w fh number of succeeding 'equal'-detections until lock table 54. mds_misccntrl1 register (address 06h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 55. mds_adjdelay register (address 08h) bit description default settings are shown highlighted. bit symbol access value description 6 to 0 mds_adjdelay[6:0] r - ac tual value adjustment delay table 56. mds_status0 register (address 09h) bit description default settings are shown highlighted. bit symbol access value description 7 early r early signal (sampled) from early-late detector 0false 1true 6 late r late signal (sampled) from early-late detector 0false 1true 5 equal r equal signal (sampled) from early-late detector 0false 1true 4 mds_lock r result equal check 0false 1true 3 early_error r adjustment delay maximum value stops the search 0false 1true 2 late_error r adjustment delay mi nimum value stops the search 0false 1true 1 equal_found r evaluation logic has detected equal condition 0false 1true 0 mds_active r evaluation logic active 0false 1true dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 50 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 57. mds_status1 register (address 0ah) bit description default settings are shown highlighted. bit symbol access value description 3 jd_odd r mds start mode 0 mds start aligned to cdi-even sample 1 mds start aligned to cdi-odd sample (only for ^2) 2 mds_prerun r mds pre-run phase active flag 0false 1true 1 mds_lockout r mds lockout detected flag 0false 1true 0 mds_lock r mds lock flag 0false 1true table 58. page_address register (a ddress 1fh) bit description default settings are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w 0h page address xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 51 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.5 page 2 allocation map description table 59. page 2 register allocation map address register name r/w bit definition default b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h maincontrol r/w - - full_re_ init sync_init_ level 0 0 force_ reset_ dclk force_ reset_ fclk 00000011 03h 3 03h jclk_cntrl r/w sr_cdi - cdi_mode[1:0] - fclk_pol fclk_sel[1:0] 00000000 00h 4 04h rst_ext_fclk r/w rst_ext_fclk_time[7:0] 00111111 3fh 5 05h rst_ext_dclk r/w rst_ext_dclk_time[7:0] 00100000 20h 6 06h dcsmu_predivcnt r/w dcsmu_p redivider[7:0] 00011110 1eh 7 07h pll_chargetime r/w pll_ charge_time[7:0] 00110010 32h 8 08h pll_run_in_time r/w pll_runin_time[7:0] 00110010 32h 9 09h ca_run_in_time r/w ca_runin_time[7:0] 00000100 04h 22 16h set_vcm_voltage r/w - - - - set_vcm[3:0] 00000010 02h 23 17h set_sync r/w - set_sync_vcom[2 :0] - set_sync_level[2:0] 01000011 43h 27 1bh type_id r dac frontend[1:0] du al dsp bit_res[1:0] 11011111 dfh 28 1ch dac_version r dac_version_id[7:0] 00000001 01h 29 1dh dig_version r dig_version_id[7:0] 00000010 02h 30 1eh jrx_ana_version r jrx_a na_version_id[7:0] 00000010 02h 31 1fh page_address r/w - - - - - page[2:0] 00000000 00h dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 52 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.6 page 2 bit definition detailed description please refer to ta b l e 5 9 for a register overview and their default values. in the following tables, all the values emphasized in bold are the default values. table 60. maincontrol register (address 00h) bit description default settings are shown highlighted. bit symbol access value description 5 full_re_init r/w initialization 0 quick reinitialization 1 full reinitialization 4 sync_init_level r/ w synchronization 0 synchronization starts with '0' 1 synchronization starts with '1' 3 - r/w must be written with ?0? 2 - r/w must be written with ?0? 1 force_reset_dclk r/w reset_dclk 0 release reset_dclk 1 force reset_dclk 0 force_reset_fclk r/w reset_fclk 0 release reset_fclk 1 force reset_fclk table 61. jclk_cntrl register (address 03h) bit description default settings are shown highlighted. bit symbol access value description 7 sr_cdi r/w cdi reset 0 no action 1 soft reset cdi 5 to 4 cdi_mode[1:0] r/w cdi mode 00 cdi_mode 0 (^2 modes) 01 cdi_mode 1 (^4 modes) 10 cdi_mode 2 (^8 modes) 11 reserved 2 fclk_pol r/w f clk polarity 0 no action 1 invert polarity 1 to 0 fclk_sel[1:0] r/w f clk clock source 00 dclk 2 01 dclk 10 dclk_div2; running 11 dclk_div2; reset dclk_div2 divider dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 53 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 62. rst_ext_fclk register (address 04h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 rst_ext_fclk_time[7 :0] r/w 3fh specifies extensi on time reset_fclk in f clk periods table 63. rst_ext_dclk register (address 05h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 rst_ext_dclk_time[7:0] r/w 20h specifies ex tension time reset_dclk (in dclk-periods) table 64. dcsmu_predivcnt register (address 06h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 dcsmu_predivider[7:0] r/w 1eh value used by dcsmu predivider (at f clk ) table 65. pll_chargetime register (address 07h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pll_charge_time[7:0] r/w 32h pll charge time (at f clk /dcsmu_predivider[7:0]) table 66. pll_run_in_time register (address 08h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 pll_runin_time[7:0] r/w 32h pll run in time (at f clk /dcsmu_predivider[7:0]) table 67. ca_run_in_time register (address 09h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ca_runin_time[7:0] r/w 04h clock alignment run in time (at f clk /dcsmu_predivider[7:0]) table 68. set_vcm_voltage register (address 16h) bit description default settings are shown highlighted. bit symbol access value description 3 to 0 set_vcm[3:0] r/w 02h set lane common-mode voltage (see table 75 ) table 69. set_sync register (address 17h) bit description default settings are shown highlighted. bit symbol access value description 6 to 4 set_sync_vcom[2:0] r/w 4h set synchronization transmitter common-mode level (see table 76 ) 2 to 0 set_sync_level[2:0] r/w 3h set synchro nization transmitter output level swing (see table 77 ) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 54 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 70. type_id register (add ress 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 dac r part type 0adc 1 dac 6 to 5 frontend [1:0] r input format 00 cmos 01 lvds 10 jesd204a 11 reserved 4 dual r converter structure 0 single 1dual 3 to 2 dsp r digital processing 00 none 01 upsampling filters 10 single sideband modulator 11 upsampling filters + single sideband modulator 1 to 0 bit_res[1:0] r resolution 00 16 bits 01 14 bits 10 12 bits 11 10 bits table 71. dac_version register (address 1ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 dac_version_id[7:0] r 01h dual dac core version table 72. dig_version register (address 1dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 dig_version_id[7:0] r 02h digital version table 73. jrx_ana_version register (address 1eh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 jrx_ana_version_id[7:0] r 02h analog deserializer version table 74. page_address register (a ddress 1fh) bit description default settings are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w 0h page address dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 55 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 75. lane common-mode voltage adjustment register 16h: set_vcm_voltage decimal set_vcm_voltage v com (v) 15 1111 1.40 14 1110 1.36 13 1101 1.31 12 1100 1.26 11 1011 1.21 10 1010 1.16 9 1001 1.12 8 1000 1.07 701111.02 601100.97 5 0101 0.92 4 0100 0.87 3 0011 0.82 2 0010 0.78 1 0001 0.73 0 0000 0.68 table 76. sync common-mode voltage adjustment register 17h: set_sync decimal set_sync_vcom[2:0] v com (v) 71111.46 6 110 1.36 5 101 1.27 4 100 1.17 30111.07 2 010 0.98 1 001 0.88 0 000 0.79 table 77. sync swing voltage adjustment register 17h: set_sync decimal set_sync_level[2:0] single-ended output voltage (v) 7 111 0.48 6 110 0.42 5 101 0.36 4 100 0.30 3 011 0.24 2 010 0.18 1 001 0.12 0 000 0.06 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 56 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.7 page 4 allocation map description table 78. page 4 register allocation map address register name r/w bit definition default b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h sr_dlp_0 r/w sr_swa_ ln3 sr_swa_ ln2 sr_swa_ ln1 sr_swa_ ln0 sr_ca_ln3 sr_ca_ln2 sr_ca_ln1 sr_ca_ln0 00000000 00h 1 01h sr_dlp_1 r/w sr_cntrl _ln3 sr_cntrl _ln2 sr_cntrl_ ln1 sr_cntrl_ ln0 sr_dec_ ln3 sr_dec_ ln2 sr_dec_ ln1 sr_dec_ ln0 00000000 00h 2 02h force_lock r/w force_ lock_ln3 force_ lock_ln2 force_ lock_ln1 force_ lock_ln0 - - - sr_ila 00000000 00h 3 03h man_lock_ ln_1_0 r/w man_lock_ln1[3:0] man_lock_ln0[3:0] 00000000 00h 4 04h man_lock_2_0 r/w man_lock_ln3[ 3:0] man_lock_ln2[3:0] 00000000 00h 5 05h ca_cntrl r/w word_ swap_ln3 word_ swap_ln2 word_ swap_ln1 word_ swap_ln0 select_rf _f10_ln3 select_rf _f10_ln2 select_rf _f10_ln1 select_rf _f10_ln0 00000000 00h 6 06h scr-cntrl r/w man_scr _ln3 man_scr_ ln2 man_scr_ ln1 man_scr_ ln0 force_ scr_ln3 force_ scr_ln2 force_ scr_ln1 force_ scr_ln0 00000000 00h 7 07h ila_cntrl r/w sel_421_ 211 sel_ila[1:0] sel_lock[2:0] sup_lane_ syn en_scr 10000011 83h 8 08h force_align r/w - - - - - - dyn_align _ena force_ align 00000000 00h 9 09h man_align_ ln_0_1 r/w man_align_ln1[3:0] man_align_ln0[3:0] 00000000 00h 10 0ah man_align_ ln_2_3 r/w man_align_ln3[3:0] man_align_ln2[3:0] 00000000 00h 11 0bh fa_err_ handling r/w sel_kout_unexp_ ln23[1:0] sel_kout_unexp_ ln10[1:0] sel_nit_err_ln23[1:0] sel_nit_err_ln10[1:0] 00000000 00h 12 0ch syncout_ mode r/w sel_re_init[2:0] sync_ pol sel_sync[3:0] 00000000 00h 13 0dh lane_ polarity r/w - - - - pol_ln3 pol_ln2 pol_ln1 pol_ln0 00000000 00h 14 0eh lane_select r/w lane_sel_ln3[1:0] lane_sel_ln2 [1:0] lane_sel_ln1[1:0] lane_sel_ln0[1:0] 11100100 e4h 16 10h soft_reset_ scrambler r/w - - - - sr_scr_ ln3 sr_scr_ ln2 sr_scr_ ln1 sr_scr_ ln0 00000000 00h 17 11h init_scr_s15t8 _ln0 r/w init_value_s15_s8_ln0[7:0] 00000000 00h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 57 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 18 12h init_scr_ s7t1_ln0 r/w - init_value_s7_s1_ln0[6:0] 00000000 00h 19 13h init_scr_ s15t8_ln1 r/w init_value_s15_s8_ln1[7:0] 00000000 00h 20 14h init_scr_ s7t1_ln1 r/w - init_value_s7_s1_ln1[6:0] 00000000 00h 21 15h init_scr_ s15t8_ln2 r/w init_value_s15_s8_ln2[7:0] 00000000 00h 22 16h init_scr_ s7t1_ln2 r/w - init_value_s7_s1_ln2[6:0] 00000000 00h 23 17h init_scr_ s15t8_ln3 r/w init_value_s15_s8_ln3[7:0] 00000000 00h 24 18h init_scr_ s7t1_ln3 r/w - init_value_s7_s1_ln3[6:0] 00000000 00h 25 19h init_ila_ bufptr_ln01 r/w init_ila_bufptr_ln1[3:0] init_ila_bufptr_ln0[3:0] 10001000 88h 26 1ah init_ila_ bufptr_ln23 r/w init_ila_bufptr_ln3[3:0] init_ila_bufptr_ln2[3:0] 10001000 88h 27 1bh error_ handling r/w - nad_err_ corr kux_corr nad_corr corr_mode[1:0] impl_alt ignore_ err 00000000 00h 28 1ch reinit_cntrl r/w reinit_ ila_ln3 reinit_ila _ln2 reinit_ila_ ln1 reinit_ila_ ln0 resync_o _l_ln3 resync_o _l_ln2 resync_o _l_ln1 resync_o _l_ln0 00000000 00h 31 1fh page_address r/w - - - - - page[2:0] 00000000 00h table 78. page 4 register allocation map ?continued address register name r/w bit definition default b7 b6 b5 b4 b3 b2 b1 b0 bin hex dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 58 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.8 page 4 bit definition detailed description please refer to ta b l e 7 8 for a register overview and their default values. in the following tables, all the values emphasized in bold are the default values. table 79. sr_dlp_0 register (address 00h) bit description default settings are shown highlighted. bit symbol access value description 7 sr_swa_ln3 r/w 0 soft reset sync_word_alignment lane 3 6 sr_swa_ln2 r/w 0 soft reset sync_word_alignment lane 2 5 sr_swa_ln1 r/w 0 soft reset sync_word_alignment lane 1 4 sr_swa_ln0 r/w 0 soft reset sync_word_alignment lane 0 3 sr_ca_ln3 r/w 0 soft reset clock_alignment lane 3 2 sr_ca_ln2 r/w 0 soft reset clock_alignment lane 2 1 sr_ca_ln1 r/w 0 soft reset clock_alignment lane 1 0 sr_ca_ln0 r/w 0 soft reset clock_alignment lane 0 table 80. sr_dlp_1 register (address 01h) bit description default settings are shown highlighted. bit symbol access value description 7 sr_cntrl_ln3 r/w 0 soft reset controller lane 3 6 sr_cntrl_ln2 r/w 0 soft reset controller lane 2 5 sr_cntrl_ln1 r/w 0 soft reset controller lane 1 4 sr_cntrl_ln0 r/w 0 soft reset controller lane 0 3 sr_dec_ln3 r/w 0 soft reset decoder_10b8b lane 3 2 sr_dec_ln2 r/w 0 soft reset decoder_10b8b lane 2 1 sr_dec_ln1 r/w 0 soft reset decoder_10b8b lane 1 0 sr_dec_ln0 r/w 0 soft reset decoder_10b8b lane 0 table 81. force_lock register (address 02h) bit description default settings are shown highlighted. bit symbol access value description 7 force_lock_ln3 r/w lane 3 lock mode 0 automatic lock sync_word_alignment lane 3 1 manual lock sync_word_alignment lane 3 6 force_lock_ln2 r/w lane 2 lock mode 0 automatic lock sync_word_alignment lane 2 1 manual lock sync_word_alignment lane 2 5 force_lock_ln1 r/w lane 1 lock mode 0 automatic lock sync_word_alignment lane 1 1 manual lock sync_word_alignment lane 1 4 force_lock_ln0 r/w lane 0 lock mode 0 automatic lock sync_word_alignment lane 0 1 manual lock sync_word_alignment lane 0 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 59 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 0 sr_ila r/w soft reset inter-lane alignment 0 no action 1 reset table 81. force_lock register (address 02h) bit description ?continued default settings are shown highlighted. bit symbol access value description table 82. man_lock_ln_1_0 register (address 03h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 man_lock_ln1[3:0] r/w 0h manual lock setting synchronization word alignment lane 1 3 to 0 man_lock_ln0[3:0] r/w 0h manual lock setting synchronization word alignment lane 0 table 83. man_lock_2_0 register (address 04h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 man_lock_ln3[3:0] r/w 0h manual lock setting synchronization word alignment lane 3 3 to 0 man_lock_ln2[3:0] r/w 0h manual lock setting synchronization word alignment lane 2 table 84. ca_cntrl register (address 05h) bit description bit symbol access value description 7 word_swap_ln3 r/w lane 3 bit swapping 0 dout_ca_ln3[7:0] = din_ca_ln3[7:0] 1 dout_ca_ln3[7:0] = din_ca_ln3[0:7] 6 word_swap_ln2 r/w lane 2 bit swapping 0 dout_ca_ln2[7:0] = din_ca_ln2[7:0] 1 dout_ca_ln2[7:0] = din_ca_ln2[0:7] 5 word_swap_ln1 r/w lane 1 bit swapping 0 dout_ca_ln1[7:0] = din_ca_ln1[7:0] 1 dout_ca_ln1[7:0] = din_ca_ln1[0:7] 4 word_swap_ln0 r/w lane 0 bit swapping 0 dout_ca_ln0[7:0] = din_ca_ln0[7:0] 1 dout_ca_ln0[7:0] = din_ca_ln0[0:7] 3 select_rf_f10_ln3 r/w lane 3 sampling mode 0 din_ca_ln3 sampled at falling edge f10_ln3 1 din_ca_ln3 sampled at rising edge f10_ln3 2 select_rf_f10_ln2 r/w lane 2 sampling mode 0 din_ca_ln2 sampled at falling edge f10_ln2 1 din_ca_ln2 sampled at rising edge f10_ln2 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 60 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 1 select_rf_f10_ln1 r/w lane 1 sampling mode 0 din_ca_ln1 sampled at falling edge f10_ln1 1 din_ca_ln1 sampled at rising edge f10_ln1 0 select_rf_f10_ln0 r/w lane 0 sampling mode 0 din_ca_ln0 sampled at falling edge f10_ln0 1 din_ca_ln0 sampled at rising edge f10_ln0 table 84. ca_cntrl register (address 05h) bit description ?continued bit symbol access value description table 85. scr_cntrl register (address 06h) bit description bit symbol access value description 7 man_scr_ln3 r/w lane 3 manual scrambling 0 scrambling lane 3 off (when force_scr_ln3 = 1) 1 scrambling lane 3 on (when force_scr_ln3 = 1) 6 man_scr_ln2 r/w lane 2 manual scrambling 0 scrambling lane 2 off (when force_scr_ln2 = 1) 1 scrambling lane 2 on (when force_scr_ln2 = 1) 5 man_scr_ln1 r/w lane 1 manual scrambling 0 scrambling lane 1 off (when force_scr_ln1 = 1) 1 scrambling lane 1 on (when force_scr_ln1 = 1) 4 man_scr_ln0 r/w lane 0 manual scrambling 0 scrambling lane 0 off (when force_scr_ln0 = 1) 1 scrambling lane 0 on (when force_scr_ln0 = 1) 3 force_scr_ln3 r/w lane 3 scrambling mode 0 scrambling lane 3 depends on lock_ln3 and en_scr 1 scrambling lane 3 depends on man_scr_ln3 2 force_scr_ln2 r/w lane 2 scrambling mode 0 scrambling lane 2 depends on lock_ln2 and en_scr 1 scrambling lane 2 depends on man_scr_ln2 1 force_scr_ln1 r/w lane 1 scrambling mode 0 scrambling lane 1 depends on lock_ln1 and en_scr 1 scrambling lane 1 depends on man_scr_ln1 0 force_scr_ln0 r/w lane 0 scrambling mode 0 scrambling lane 0 depends on lock_ln0 and en_scr 1 scrambling lane 0 depends on man_scr_ln0 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 61 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 86. ila_cntrl register (address 07h) bit description bit symbol access value description 7 sel_421_211 r/w inter-lane alignment mode 0 inter-lane alignment based on lane 3 : lane 2 and/or lane 1 : lane 0 1 inter-lane alignment based on ln3 : ln0 6 to 5 sel_ila[1:0] r/w inter-lane alignment trigger mode 00 inter-lane alignment is done after receiving 1/a/-symbol 01 inter-lane alignment is done after receiving 2 /a/ symbols 10 inter-lane alignment is done after receiving 3 /a/ symbols 11 inter-lane alignment is done after receiving 4 /a/ symbols 4 to 2 sel_lock[2:0] r/w inter-lane alignment start mode 000 inter-lane alignment may start only if all (4 or 2) lanes are locked 001 inter-lane alignment may start if one of the (4 or 2) lanes are locked 010 inter-lane alignment may start if lane 0 is locked 011 inter-lane alignment may start if lane 1 is locked 100 inter-lane alignment may start if lane 2 is locked 101 inter-lane alignment may start if lane 3 is locked 1 sup_lane_syn r/w inter-lane alignment enable 0 inter-lane alignment synchronization disabled 1 inter-lane alignment synchronization enabled 0 en_scr r/w data descrambling 0 disabled 1 enabled table 87. force_align register (address 08h) bit description bit symbol access value description 1 dyn_align_ena r/w dynamic re-alignment mode 0 no dynamic re-alignment 1 dynamic re-alignment (and monitoring) enabled 0 force_align r/w lane alignment mode 0 automatic lane alignment based on /a/ symbols 1 manual lane alignment based on man_align_lnx table 88. man_align_ln_0_1 register (address 09h) bit description bit symbol access value description 7 to 4 man_align_ln1[3:0] r/w 0h indicates alignment data-delay for lane 1 [1..15] 3 to 0 man_align_ln0[3:0] r/w 0h indicates alignment data-delay for lane 0 [1..15] dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 62 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 89. man_align_ln_2_3 register (address 0ah) bit description bit symbol access value description 7 to 4 man_align_ln3[3:0] r/w 0h indicates alignment data-delay for lane 3 [1..15] 3 to 0 man_align_ln2[3:0] r/w 0h indicates alignment data-delay for lane 2 [1..15] table 90. fa_err_handling register (address 0bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 sel_kout_ unexp_ln23[1:0] r/w lane 2/lane 3 unexpected /k/ error handling 00 unexpected /k/ in lane 2 or lane 3 error_handling 01 unexpected /k/ in lane 2 and lane 3 error_handling 10 unexpected /k/ in lane 2 error_handling 11 unexpected /k/ in lane 3 error_handling 5 to 4 sel_kout_ unexp_ln10[1:0] r/w lane 0/lane 1 unexpected /k/ error handling 00 unexpected /k/ in lane 0 or lane 1 error_handling 01 unexpected /k/ in lane 0 and lane 1 error_handling 10 unexpected /k/ in lane 0 error_handling 11 unexpected /k/ in lane 1 error_handling 3 to 2 sel_nit_err_ ln23[1:0] r/w lane 2/lane 3 nit-error handling 00 nit-errors in lane 2 or lane 3 error_handling 01 not-in-table errors lane 2 and lane 3 error_handling 10 not-in-table errors in lane 2 error_handling 11 not-in-table errors in lane 3 error_handling 1 to 0 sel_nit_err_ ln10[1:0] r/w lane 0/lane 1 nit-error handling 00 nit-errors in lane 0 or lane 1 error_handling 01 not-in-table errors lane 0 and lane 1 error_handling 10 not-in-table errors in lane 0 error_handling 11 not-in-table errors in lane 1 error_handling dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 63 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 91. syncout_mode register (address 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 5 sel_re_init[2:0] r /w reinitialization mode 000 i_re_init when 1 of the lane_rst's is active 001 i_re_init when rst_ln0 or rst_ln1 is active 010 i_re_init when rst_ln2 or rst_ln3 is active 011 i_re_init when rst_ln0 is active 100 i_re_init when rst_ln1 is active 101 i_re_init when rst_ln2 is active 110 i_re_init when rst_ln3 is active 111 i_re_init remains '0' 4 sync_pol r/w synchronization polarity 0 sync_out is active when low 1 sync_out is active when high 3 to 0 sel_sync[3:0] r/w synchronization mode 0000 sync when one of the four lane_syncs is active 0001 sync when all four lane_syncs are active 0010 sync when sync_ln0 or sync_ln1 is active 0011 sync when both sync_ln0 and sync_ln1 are active 0100 sync when sync_ln2 or sync_ln3 is active 0101 sync when both sync_ln2 and sync_ln3 are active 0110 sync when sync_ln0 is active 0111 sync when sync_ln1 is active 1000 sync when sync_ln2 is active 1001 sync when sync_ln3 is active 1010 sync remains fixed '1' other sync remains fixed '0' table 92. lane_polarity register (address 0dh) bit description bit symbol access value description 3 pol_ln3 r/w lane 3 data polarity 0 no action 1 invert all data bits of lane 3 2 pol_ln2 r/w lane 2 data polarity 0 no action 1 invert all data bits of lane 2 1 pol_ln1 r/w lane 1 data polarity 0 no action 1 invert all data bits of lane 1] 0 pol_ln0 r/w lane 0 data polarity 0 no action 1 invert all data bits of lane 0 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 64 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 93. lane_select register (address 0eh) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 lane_sel_ln3[1:0] r/w lane 3 data mapping 00 ila_in_ln3 = lane_ln0 (dout and controls) 01 ila_in_ln3 = lane_ln1 (dout and controls) 10 ila_in_ln3 = lane_ln2 (dout and controls) 11 ila_in_ln3 = lane_ln3 (dout and controls) 5 to 4 lane_sel_ln2[1:0] r/w lane 2 data mapping 00 ila_in_ln2 = lane_ln0 (dout and controls) 01 ila_in_ln2 = lane_ln1 (dout and controls) 10 ila_in_ln2 = lane_ln2 (dout and controls) 11 ila_in_ln2 = lane_ln3 (dout and controls) 3 to 2 lane_sel_ln1[1:0] r/w lane 1 data mapping 00 ila_in_ln1 = lane_ln0 (dout and controls) 01 ila_in_ln1 = lane_ln1 (dout and controls) 10 ila_in_ln1 = lane_ln2 (dout and controls) 11 ila_in_ln1 = lane_ln3 (dout and controls 1 to 0 lane_sel_ln0[1:0] r/w lane 0 data mapping 00 ila_in_ln0 = lane_ln0 (dout and controls) 01 ila_in_ln0 = lane_ln1 (dout and controls) 10 ila_in_ln0 = lane_ln2 (dout and controls) 11 ila_in_ln0 = lane_ln3 (dout and controls) table 94. soft_reset_scrambler regist er (address 10h) bit description bit symbol access value description 3 sr_scr_ln3 r/w lane 3 scrambler reset 0 no action 1 soft_reset scrambler of lane 3 2 sr_scr_ln2 r/w lane 2 scrambler reset 0 no action 1 soft_reset scrambler of lane 2 1 sr_scr_ln1 r/w lane 1 scrambler reset 0 no action 1 soft_reset scrambler of lane 1 0 sr_scr_ln0 r/w lane 0 scrambler reset 0 no action 1 soft_reset scrambler of lane 0 table 95. init_scr_s15t8_ln0 register (address 11h) bit description bit symbol access value description 7 to 0 init_value_s15_s8_ln0[7:0] r/w 00h initia lization value for lane 0 descrambler bits s15 : s8 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 65 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 96. init_scr_s7t1_ln0 (address 12h) bit description bit symbol access value description 6 to 0 init_value_s7_s1_ln0[6:0] r/w 00h initializat ion value for lane 0 descrambler bits s7 : s1 table 97. init_scr_s15t8_ln1 register (address 13h) bit description bit symbol access value description 7 to 0 init_value_s15_s8_ln1[7:0] r/w 00h initia lization value for lane 1 descrambler bits s15 : s8 table 98. init_scr_s7t1_ln1 register (address 14h) bit description bit symbol access value description 6 to 0 init_value_s7_s1_ln1[6:0] r/w 00h initializat ion value for lane 1 descrambler bits s7 : s1 table 99. init_scr_s15t8_ln2 register (address 15h) bit description bit symbol access value description 7 to 0 init_value_s15_s8_ln2[7:0] r/w 00h initia lization value for lane 2 descrambler bits s15 : s8 table 100. init_scr_s7t1_ln2 register (address 16h) bit description bit symbol access value description 6 to 0 init_value_s7_s1_ln2[6:0] r/w 00h initializat ion value for lane 2 descrambler bits s7 : s1 table 101. init_scr_s15t8_ln3 register (address 17h) bit description bit symbol access value description 7 to 0 init_value_s15_s8_ln3[7:0] r/w 00h initia lization value for lane 3 descrambler bits s15 : s8 table 102. init_scr_s7t1_ln3 register (address 18h) bit description bit symbol access value description 6 to 0 init_value_s7_s1_ln3[6:0] r/w 00h initializat ion value for lane 3 descrambler bits s7 : s1 table 103. init_ila_bufptr_ln01 register (address 19h) bit description bit symbol access value description 7 to 4 init_ila_bufptr_ln1[3:0] r/w 8h initialization value for lane 1 ila buffer pointer 3 to 0 init_ila_bufptr_ln0[3:0] r/w 8h initialization value for lane 0 ila buffer pointer table 104. init_ila_bufptr_ln23 register (address 1ah) bit description bit symbol access value description 7 to 4 init_ila_bufptr_ln3[3:0] r/w 8h initialization value for lane 3 ila buffer pointer 3 to 0 init_ila_bufptr_ln2[3:0] r/w 8h initialization value for lane 2 ila buffer pointer dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 66 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 105. error_handling register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 6 nad_err_corr r/w frame assembler (fa) 0 not-in-table errors passed to fa 1 nad (nit and disparity) errors passed to fa 5 kux_corr r/w k-character error mode 0 unexpected k-character errors ignored (at fa) 1 unexpected k-character errors concealment (at fa) 4 nad_corr r/w nad error mode 0 nad-errors ig nored (at fa) 1 nad-errors concealment (at fa) 3 to 2 corr_mode[1:0] r/w conceal mode 00 conceal 1 period at fa 01 conceal 2 periods at fa 10 conceal 3 periods at fa 11 conceal 4 periods at fa 1 impl_alt r/w disparity error detection configuration 0 default disparity error detection (table mode) 1 alternative disparity error detection (cnt mode) 0 ignore_err r/w general error mode 0 no action 1 ignore disparity/nit-errors at lane-controller table 106. reinit_cntrl register (address 1ch) bit description default settings are shown highlighted. bit symbol access value description 7 reinit_ila_ln3 r/w lane 3, ila-buffer out-of-range check 0 no action 1 lane 3 ila-buffer out-of-range_error will activate reinitialization 6 reinit_ila_ln2 r/w lane 2, ila-buffer out-of-range check 0 no action 1 lane 2 ila-buffer out-of-range_error will activate reinitialization 5 reinit_ila_ln1 r/w lane 1, ila-buffer out-of-range check 0 no action 1 lane 1 ila-buffer out-of-range_error will activate reinitialization 4 reinit_ila_ln0 r/w lane 0, ila-buffer out-of-range check 0 no action 1 lane 0 ila-buffer out-of-range_error will activate reinitialization dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 67 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 3 resync_o_l_ln3 r/w lane 3, resync over link 0 no action 1 lane 3 lane controller checks for k28.5 /k/ symbols 2 resync_o_l_ln2 r/w lane 2, resync over link 0 no action 1 lane 2 lane controller checks for k28.5 /k/ symbols 1 resync_o_l_ln1 r/w lane 1, resync over link 0 no action 1 lane 1 lane controller checks for k28.5 /k/ symbols 0 resync_o_l_ln0 r/w lane 0, resync over link 0 no action 1 lane 0 controller che cks for k28.5 /k/ symbols table 106. reinit_cntrl register (address 1ch) bit description ?continued default settings are shown highlighted. bit symbol access value description table 107. page_address register (address 1fh) bit description bit symbol access value description 2 to 0 page[2:0] r/w 0h page_address xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 68 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.9 page 5 allocation map description table 108. page 5 register allocation map address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h ila_mon_1_0 r ila_mon_ln1[3:0] ila_mon_ln0[3:0 uuuuuuuu uuh 1 01h ila_mon_3_2 r ila_mon_ln3[3:0] ila_mon_ln2[3:0] uuuuuuuu uuh 2 02h ila_buf_err r - - - - ila_buf_ err_ln3 ila_buf_ err_ln2 ila_buf_ err_ln1 ila_buf_ err_ln0 uuuuuuuu uuh 3 03h ca_mon r ca_mon_ln3[1:0] ca_mon_ln2[1:0 ] ca_mon_ln1[1:0] ca_mon_ln0[1:0] uuuuuuuu uuh 4 04h dec_flags r dec_nit _err_ ln3 dec_nit _err_ ln2 dec_nit_ err_ln1 dec_nit_ err_ln0 dec_disp_ err_ln3 dec_disp_ err_ln2 dec_disp_ err_ln1 dec_disp_ err_ln0 uuuuuuuu uuh 5 05h kout_flag r - - - - dec_kout_ ln3 dec_kout_ ln2 dec_kout_ ln1 dec_kout_ ln0 uuuuuuuu uuh 6 06h k28_ln0_flag r - - - k28_7_ln0 k28_5_ln0 k28_4_ln0 k28_3_ln0 k28_0_ln0 uuuuuuuu uuh 7 07h k28_ln1_flag r - - - k28_7_ln1 k28_5_ln1 k28_4_ln1 k28_3_ln1 k28_0_ln1 uuuuuuuu uuh 8 08h k28_ln2_flag r - - - k28_7_ln2 k28_5_ln2 k28_4_ln2 k28_3_ln2 k28_0_ln2 uuuuuuuu uuh 9 09h k28_ln3_flag r - - - k28_7_ln3 k28_5_ln3 k28_4_ln3 k28_3_ln3 k28_0_ln3 uuuuuuuu uuh 10 0ah kout_ unexpected_ flag r- - - -dec_kout_ unexp_ln3 dec_kout_ unexp_ln2 dec_kout_ unexp_ln1 dec_kout_ unexp_ln0 uuuuuuuu uuh 11 0bh lock_cnt_ mon_ln01 r lock_cnt_mon_ln1[3:0] lock_cnt_mon_ln0[3:0] uuuuuuuu uuh 12 0ch lock_cnt_ mon_ln23 r lock_cnt_mon_ln3[3:0] lock_cnt_mon_ln2[3:0] uuuuuuuu uuh 13 0dh cs_state_lnx r cs_state_ln3[1:0] cs_state_ln2[1:0] cs_state_ln1[1:0] cs_state_ln0[1:0] uuuuuuuu uuh 14 0eh rst_buf_err_ flags r/w rst_ buf_ err_ flags - - - - - - - 00000000 00h 15 0fh intr_misc_ ena r/w intr_ ena_ cs_ init_ln3 intr_ ena_cs_ init_ln2 intr_ena_ cs_init_ ln1 intr_ena_ cs_init_ ln0 intr_ena_ buf_err_ ln3 intr_ena_ buf_err_ ln2 intr_ena_ buf_err_ ln1 intr_ena_ buf_err_ ln0 00000000 00h 16 10h flag_cnt_lsb _ln0 r flag_cnt_ln0[7:0] uuuuuuuu uuh xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 69 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a [1] u = undefined at power-up or after reset. 17 11h flag_cnt_ msb_ln0 r flag_cnt_ln0[15:8] uuuuuuuu uuh 18 12h flag_cnt_lsb _ln1 r flag_cnt_ln1[7:0] uuuuuuuu uuh 19 13h flag_cnt_ msb_ln1 r flag_cnt_ln1[15:8] uuuuuuuu uuh 20 14h flag_cnt_lsb _ln2 r flag_cnt_ln2[7:0] uuuuuuuu uuh 21 15h flag_cnt_ msb_ln2 r flag_cnt_ln2[15:8] uuuuuuuu uuh 22 16h flag_cnt_lsb _ln3 r flag_cnt_ln3[7:0] uuuuuuuu uuh 23 17h flag_cnt_ msb_ln3 r flag_cnt_ln3[15:8] uuuuuuuu uuh 24 18h ber_level_ lsb r/w ber_level[7:0] 00000000 00h 25 19h ber_level_ msb r/w ber_level[15: 8] 00000000 00h 26 1ah intr_ena r/w intr_ ena_ nit intr_ ena_ disp intr_ena_ kout intr_ena_ kout_ unexp intr_ena_ k28_7 intr_ena_ k28_5 intr_ena_ k28_3 intr_ena_ misc 00000000 00h 27 1bh cntrl_ flagcnt_ln01 r/w rst_ cfc_ ln1 sel_cfc_ln1[2:0] rst_cfc_ ln0 sel_cfc_ln0[2:0] 01010101 55h 28 1ch cntrl_ flagcnt_ln23 r/w rst_ cfc_ln3 sel_cfc_ln3[2:0] rst_cfc_ ln2 sel_cfc_ln2[2:0] 01010101 55h 29 1dh mon_flags_ reset r/w rst_nit _err- flags rst_ disp_ err_ flags rst_kout _flags rst_kout _unexpec ted_flags rst_k28_ ln3_flags rst_k28_ ln2_flags rst_k28_ ln1_flags rst_k28_ ln0_flags 00000000 00h 30 1eh dbg_cntrl r/w ber_ mode intr_ clear intr_mode[2:0] - - - 00000000 00h 31 1fh page_ address r/w - - - - - page[2:0] 00000000 00h table 108. page 5 register allocation map ?continued address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 70 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.10 page 5 bit defi nition detailed description please refer to ta b l e 1 0 8 for a register overview and thei r default values. in the following tables, all the values emphasized in bold are the default values. table 109. ila_mon_1_0 register (address 00h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 ila_mon_ln1[3:0] r - ila_buf_ln1 pointer 3 to 0 ila_mon_ln0[3:0] r - ila_buf_ln0 pointer table 110. ila_mon_3_2 register (address 01h) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 ila_mon_ln3[3:0] r - ila_buf_ln3 pointer 3 to 0 ila_mon_ln2[3:0] r - ila_buf_ln2 pointer table 111. ila_buf_err register (address 02h) bit description default settings are shown highlighted. bit symbol access value description 3 ila_buf_err_ln3 r lane 3 ila buffer error 0 ila_buf_ln3 pointer is in range 1 ila_buf_ln3 pointer is out of range 2 ila_buf_err_ln2 r lane 2 ila buffer error 0 ila_buf_ln2 pointer is in range 1 ila_buf_ln2 pointer is out of range 1 ila_buf_err_ln1 r lane 1 ila buffer error 0 ila_buf_ln1 pointer is in range 1 ila_buf_ln1 pointer is out of range 0 ila_buf_err_ln0 r lane 0 ila buffer error 0 ila_buf_ln0 pointer is in range 1 ila_buf_ln0 pointer is out of range table 112. ca_mon register (address 03h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ca_mon_ln3[1:0] r - clock alignment phase monitor lane 3 5 to 4 ca_mon_ln2[1:0] r - clock alignment phase monitor lane 2 3 to 2 ca_mon_ln1[1:0] r - clock alignment phase monitor lane 1 1 to 0 ca_mon_ln0[1:0] r - clock alignment phase monitor lane 0 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 71 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 113. dec_flags register (address 04h) bit description bit symbol access value description 7 dec_nit_err_ln3 r - not-in-table error flag lane 3 6 dec_nit_err_ln2 r - not-in-table error flag lane 2 5 dec_nit_err_ln1 r - not-in-table error flag lane 1 4 dec_nit_err_ln0 r - not-in-table error flag lane 0 3 dec_disp_err_ln3 r - disparity error flag lane 3 2 dec_disp_err_ln2 r - disparity error flag lane 2 1 dec_disp_err_ln1 r - disparity error flag lane 1 0 dec_disp_err_ln0 r - disparity error flag lane 0 table 114. kout_flag register (address 05h) bit description bit symbol access value description 3 dec_kout_ln3 r - /k/ symbols found in lane 3 2 dec_kout_ln2 r - /k/ symbols found in lane 2 1 dec_kout_ln1 r - /k/ symbols found in lane 1 0 dec_kout_ln0 r - /k/ symbols found in lane 0 table 115. k28_ln0_flag register (address 06h) bit description bit symbol access value description 4 k28_7_ln0 r - k28_7 /f/ symbols found in lane 0 3 k28_5_ln0 r - k28_5 /k/ symbols found in lane 0 2 k28_4_ln0 r - k28_4 /q/ symbols found in lane 0 1 k28_3_ln0 r - k28_3 /a/ symbols found in lane 0 0 k28_0_ln0 r - k28_0 /r/ symbols found in lane 0 table 116. k28_ln1_flag register (address 07h) bit description bit symbol access value description 4 k28_7_ln1 r - k28_7 /f/ symbols found in lane 1 3 k28_5_ln1 r - k28_5 /k/ symbols found in lane 1 2 k28_4_ln1 r - k28_4 /q/ symbols found in lane 1 1 k28_3_ln1 r - k28_3 /a/ symbols found in lane 1 0 k28_0_ln1 r - k28_0 /r/ symbols found in lane 1 table 117. k28_ln2_flag register (address 08h) bit description bit symbol access value description 4 k28_7_ln2 r - k28_7 /f/ symbols found in lane 2 3 k28_5_ln2 r - k28_5 /k/ symbols found in lane 2 2 k28_4_ln2 r - k28_4 /q/ symbols found in lane 2 1 k28_3_ln2 r - k28_3 /a/ symbols found in lane 2 0 k28_0_ln2 r - k28_0 /r/ symbols found in lane 2 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 72 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 118. k28_ln3_flag register (address 09h) bit description bit symbol access value description 4 k28_7_ln3 r - k28_7 /f/ symbols found in lane 3 3 k28_5_ln3 r - k28_5 /k/ symbols found in lane 3 2 k28_4_ln3 r - k28_4 /q/ symbols found in lane 3 1 k28_3_ln3 r - k28_3 /a/ symbols found in lane 3 0 k28_0_ln3 r - k28_0 /r/ symbols found in lane 3 table 119. kout_unexpected_ flag regist er (address 0ah) bit description bit symbol access value description 3 dec_kout_unexp_ln3 r - unexpected /k/ symbols fo und in lane 3 2 dec_kout_unexp_ln2 r - unexpected /k/ symbols fo und in lane 2 1 dec_kout_unexp_ln1 r - unexpected /k/ symbols fo und in lane 1 0 dec_kout_unexp_ln0 r - unexpected /k/ symbols fo und in lane 0 table 120. lock_cnt_mon_ln01 register (address 0bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 lock_cnt_mon_ln1[3:0] r - lock_state monitor synchronization word alignment lane 1 3 to 0 lock_cnt_mon_ln0[3:0] r - lock_state monitor synchronization word alignment lane 0 table 121. lock_cnt_mon_ln23 register (address 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 4 lock_cnt_mon_ln3[3:0] r - lock_state monitor synchronization word alignment lane 3 3 to 0 lock_cnt_mon_ln2[3:0] r - lock_state monitor synchronization word alignment lane 2 table 122. cs_state_lnx register (address 0dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 cs_state_ln3[1:0] r - monitor cs_state fsm lane 3 (see table 142 ) 5 to 4 cs_state_ln2[1:0] r - monitor cs_state fsm lane 2 (see table 142 ) 3 to 2 cs_state_ln1[1:0] r - monitor cs_state fsm lane 1 (see table 142 ) 1 to 0 cs_state_ln0[1:0] r - monitor cs_state fsm lane 0 (see table 142 ) table 123. rst_buf_err_flags register (address 0eh) bit description default settings are shown highlighted. bit symbol access value description 7 rst_buf_err_flags r/w 0 reset ila_buf_err_lnn flags dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 73 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 124. intr_misc_ena register (address 0fh) bit description default settings are shown highlighted. bit symbol access value description 7 intr_ena_cs_init_ln3 r/w 0 intr_misc in case cs_stat e_ln3 = cs_init 6 intr_ena_cs_init_ln2 r/w 0 intr_misc in case cs_stat e_ln2 = cs_init 5 intr_ena_cs_init_ln1 r/w 0 intr_misc in case cs_stat e_ln1 = cs_init 4 intr_ena_cs_init_ln0 r/w 0 intr_misc in case cs_stat e_ln0 = cs_init 3 intr_ena_buf_err_ln3 r/w 0 generate interrupt if ila_buf_err_ln3 = 1 2 intr_ena_buf_err_ln2 r/w 0 generate interrupt if ila_buf_err_ln2 = 1 1 intr_ena_buf_err_ln1 r/w 0 generate interrupt if ila_buf_err_ln1 = 1 0 intr_ena_buf_err_ln0 r/w 0 generate interrupt if ila_buf_err_ln0 = 1 table 125. flag_cnt_lsb_ln0 register (address 10h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln0[7:0] r - lsbs of flag_counter lane 0 table 126. flag_cnt_msb_ln0 regist er (address 11h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln0[15:8] r - msbs of flag_counter lane 0 table 127. flag_cnt_lsb_ln1 register (address 12h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln1[7:0] r - lsbs of flag_counter lane 1 table 128. flag_cnt_msb_ln1 regist er (address 13h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln1[15:8] r - msbs of flag_counter lane 1 table 129. flag_cnt_lsb_ln2 register (address 14h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln2[7:0] r - lsbs of flag_counter lane 2 table 130. flag_cnt_msb_ln2 regist er (address 15h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln2[15:8] r - msbs of flag_counter lane 2 table 131. flag_cnt_lsb_ln3 register (address 16h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln3[7:0] r - lsbs of flag_counter lane 3 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 74 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 132. flag_cnt_msb_ln3 regist er (address 17h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 flag_cnt_ln3[15:8] r - msbs of flag_counter lane 3 table 133. ber_level_lsb register (address 18h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ber_level[7:0] r/w 00h lsbs level used for simple (dc) ber-measurement table 134. ber_level_msb register (address 19h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ber_level[15:8] r/w 00h msbs level used for simple (dc) ber-measurement table 135. intr_ena register (address 1ah) bit description bit symbol access value description 7 intr_ena_nit r/w not-in-table interrupt 0 no action 1 nit-error in ln dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 75 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 136. cntrl_flagcnt_ln01 register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 rst_cfc_ln1 r/w 0 reset flag_cnt_ln1 6 to 4 sel_cfc_ln1[2:0] r/w 5h select flag_cnt_ln1 source (see table 141 ) 3 rst_cfc_ln0 r/w 0 reset flag_cnt_ln0 2 to 0 sel_cfc_ln0[2:0] r/w 5h select flag_cnt_ln0 source (see table 141 ) table 137. cntrl_flagcnt_ln23 register (address 1ch) bit description default settings are shown highlighted. bit symbol access value description 7 rst_cfc_ln3 r/w 0 reset flag_cnt_ln3 6 to 4 sel_cfc_ln3[2:0] r/w 5h select flag_cnt_ln3 source (see table 141 ) 3 rst_cfc_ln2 r/w 0 reset flag_cnt_ln2 2 to 0 sel_cfc_ln2[2:0] r/w 5h select flag_cnt_ln2 source (see table 141 ) table 138. mon_flags_reset register (address 1dh) bit description bit symbol access value description 7 rst_nit_err-flags r/w 0 reset nit-error monitor flags 6 rst_disp_err_flags r/w 0 res et disparity monitor flags 5 rst_kout_flags r/w 0 reset k symbols monitor flags 4 rst_kout_unexpected_fla gs r/w 0 reset unexpected k symbols monitor flags 3 rst_k28_ln3_flags r/w 0 reset k28_x monitor flags for lane 3 2 rst_k28_ln2_flags r/w 0 reset k28_x monitor flags for lane 2 1 rst_k28_ln1_flags r/w 0 reset k28_x monitor flags for lane 1 0 rst_k28_ln0_flags r/w 0 reset k28_x monitor flags for lane 0 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 76 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 139. dbg_cntrl register (a ddress 1eh) bit description bit symbol access value description 7 ber_mode r/w simple ber-measurement 0 no action 1 simple ber-measurement enabled 6 intr_clear r/w interrupts clear 0 no action 1 clear interrupts (to '1') 5 to 3 intr_mode[2:0] r/w interrupt settings 000 global interrupt depends on lane 0 001 global interrupt depends on lane 1 010 global interrupt depends on lane 2 011 global interrupt depends on lane 3 100 global interrupt depends on lane 0 or lane 1 101 global interrupt depends on lane 2 or lane 3 110 global interrupt depends on lane 0 or lane 1 or lane 2 or lane 3 111 no interrupt table 140. page_address register (address 1fh) bit description bit symbol access value description 2 to 0 page[2:0] r/w 0h page_address table 141. counter source default settings are shown highlighted. sel_cfc_lnn[2:0] source 000 not-in-table error 001 disparity error 010 k symbol found 011 unexpected k symbol found 100 k28_7 (/f/) symbol found 101 k28_5 (/k/) symbol found 110 k28_3 (/a/) symbol found 111 k28_0 (/r/) symbol found table 142. code group synchronization state machine cs_state_lnn[1:0] definition 00 looking for k28_5 (/k/) symbol 01 four consecutive k28_5 (/k/) symbols have been received 10 code group synchronization achieved 11 not applicable xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 77 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.11 page 6 allocation map description table 143. page 6 register allocation map address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h ln0_cfg_0 r ln0_did[7:0] uuuuuuuu 0xuu 1 01h ln0_cfg_1 r - - - - ln0_bid[3:0] uuuuuuuu 0xuu 2 02h ln0_cfg_2 r - - - ln0_lid[4:0] uuuuuuuu 0xuu 3 03h ln0_cfg_3 r ln0_scr - - ln0_l[4:0] uuuuuuuu 0xuu 4 04h ln0_cfg_4 r ln0_f[7:0] uuuuuuuu 0xuu 5 05h ln0_cfg_5 r - - - ln0_k[4:0] uuuuuuuu 0xuu 6 06h ln0_cfg_6 r ln0_m[7:0] uuuuuuuu 0xuu 7 07h ln0_cfg_7 r ln0_cs[1:0] - ln0_n[4:0] uuuuuuuu 0xuu 8 08h ln0_cfg_8 r - - - ln0_n?[4:0] uuuuuuuu 0xuu 9 09h ln0_cfg_9 r - - - ln0_s[4:0] uuuuuuuu 0xuu 10 0ah ln0_cfg_10 r ln0_hd - - ln0_cf[4:0] uuuuuuuu 0xuu 11 0bh ln0_cfg_11 r ln0_res1[7:0] uuuuuuuu 0xuu 12 0ch ln0_cfg_12 r ln0_res2[7:0] uuuuuuuu 0xuu 13 0dh ln0_cfg_13 r ln0_fchk[7:0] uuuuuuuu 0xuu 16 10h ln1_cfg_0 r ln1_did[7:0] uuuuuuuu 0xuu 17 11h ln1_cfg_1 r - - - - ln1_bid[3:0] uuuuuuuu 0xuu 18 12h ln1_cfg_2 r - - - ln1_lid[4:0] uuuuuuuu 0xuu 19 13h ln1_cfg_3 r ln1_scr - - ln1_l[4:0] uuuuuuuu 0xuu 20 14h ln1_cfg_4 r ln1_f[7:0] uuuuuuuu 0xuu 21 15h ln1_cfg_5 r - - - ln1_k[4:0] uuuuuuuu 0xuu 22 16h ln1_cfg_6 r ln1_m[7:0] uuuuuuuu 0xuu 23 17h ln1_cfg_7 r ln1_cs[1:0] - ln1_n[4:0] uuuuuuuu 0xuu 24 18h ln1_cfg_8 r - - - ln1_n?[4:0] uuuuuuuu 0xuu 25 19h ln1_cfg_9 r - - - ln1_s[4:0] uuuuuuuu 0xuu 26 1ah ln1_cfg_10 r ln1_hd - - ln1_cf[4:0] uuuuuuuu 0xuu 27 1bh ln1_cfg_11 r ln1_res1[7:0] uuuuuuuu 0xuu xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 78 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a [1] u = undefined at power-up or after reset. 28 1ch ln1_cfg_12 r ln1_res2[7:0] uuuuuuuu 0xuu 29 1dh ln1_cfg_13 r ln1_fchk[7:0] uuuuuuuu 0xuu 31 1fh page_address r/w - - - - - page[2:0] 00000000 00h table 143. page 6 register allocation map ?continued address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 79 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.12 page 6 bit defi nition detailed description please refer to ta b l e 1 4 3 for a register overview and thei r default values. in the following tables, all the values emphasized in bold are the default values. table 144. ln0_cfg_0 register (a ddress 00h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln0_did[7:0] r - lane 0 device id table 145. ln0_cfg_1 register (a ddress 01h) bit description default settings are shown highlighted. bit symbol access value description 3 to 0 ln0_bid[3:0] r - lane 0 bank id table 146. ln0_cfg_2 register (a ddress 02h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln0_lid[4:0] r - lane 0 lane id table 147. ln0_cfg_3 register (a ddress 03h) bit description default settings are shown highlighted. bit symbol access value description 7 ln0_scr r - scrambling on 4 to 0 ln0_l[4:0] r - number of lanes minus 1 table 148. ln0_cfg_4 register (a ddress 04h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln0_f[7:0] r - number of octets per frame minus 1 table 149. ln0_cfg_5 register (a ddress 05h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln0_k[4:0] r - number of frames per multi-frame minus 1 table 150. ln0_cfg_6 register (a ddress 06h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln0_m[7:0] r - number of converters per device minus 1 table 151. ln0_cfg_7 register (a ddress 07h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ln0_cs[1:0] r - number of control bits 4 to 0 ln0_n[4:0] r - converter resolution minus 1 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 80 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 152. ln0_cfg_8 register (a ddress 08h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln0_n?[4:0] r - number of bits per sample minus 1 table 153. ln0_cfg_9 register (a ddress 09h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln0_s[4:0] r - number of samples per converter per frame cycle minus 1 table 154. ln0_cfg_10 register (a ddress 0ah) bit description default settings are shown highlighted. bit symbol access value description 7 ln0_hd r - high density 4 to 0 ln0_cf[4:0] r - number of control words per frame cycle table 155. ln0_cfg_11 register (address 0bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln0_res1[7:0] r - lane 0 reserved field table 156. ln0_cfg_12 register (a ddress 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln0_res2[7:0] r - lane 0 reserved field table 157. ln0_cfg_13 register (a ddress 0dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln0_fchk[7:0] r - lane 0 checksum table 158. ln1_cfg_0 register (a ddress 10h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln1_did[7:0] r - lane 1 device id table 159. ln1_cfg_1 register (address 11h) bit description default settings are shown highlighted. bit symbol access value description 3 to 0 ln1_bid[3:0] r - lane 1 bank id table 160. ln1_cfg_2 register (a ddress 12h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln1_lid[4:0] r - lane 1 lane id dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 81 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 161. ln1_cfg_3 register (a ddress 13h) bit description default settings are shown highlighted. bit symbol access value description 7 ln1_scr r - scrambling on 4 to 0 ln1_l[4:0] r - number of lanes minus 1 table 162. ln1_cfg_4 register (a ddress 14h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln1_f[7:0] r - number of octets per frame minus 1 table 163. ln1_cfg_5 register (a ddress 15h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln1_k[4:0] r - number of frames per multiframe minus 1 table 164. ln1_cfg_6 register (a ddress 16h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln1_m[7:0] r - number of converters per device minus 1 table 165. ln1_cfg_7 register (a ddress 17h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ln1_cs[1:0] r - number of control bits 4 to 0 ln1_n[4:0] r - converter resolution minus 1 table 166. ln1_cfg_8 register (a ddress 18h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln1_n?[4:0] r - number of bits per sample minus 1 table 167. ln1_cfg_9 register (a ddress 19h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln1_s[4:0] r - number of samples per converter per frame cycle minus 1 table 168. ln1_cfg_10 register (a ddress 1ah) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ln1_hd r - high density 4 to 0 ln1_cf[4:0] r - number of control words per frame cycle dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 82 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 169. ln1_cfg_11 register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln1_res1[7:0] r - lane 1 reserved field table 170. ln1_cfg_12 register (a ddress 1ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln1_res2[7:0] r - lane 1 reserved field table 171. ln1_cfg_13 register (a ddress 1dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln1_fchk[7:0] r - lane 1 checksum table 172. page_address register (address 1fh) bit description default settings are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w 0h page_address xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 83 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.13 page 7 allocation map description table 173. page 7 register allocation map address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex 0 00h ln2_cfg_0 r ln2_did[7:0] uuuuuuuu 0xuu 1 01h ln2_cfg_1 r - - - - ln2_bid[3:0] uuuuuuuu 0xuu 2 02h ln2_cfg_2 r - - - ln2_lid[4:0] uuuuuuuu 0xuu 3 03h ln2_cfg_3 r ln2_scr - - ln2_l[4:0] uuuuuuuu 0xuu 4 04h ln2_cfg_4 r ln2_f[7:0] uuuuuuuu 0xuu 5 05h ln2_cfg_5 r - - - ln2_k[4:0] uuuuuuuu 0xuu 6 06h ln2_cfg_6 r ln2_m[7:0] uuuuuuuu 0xuu 7 07h ln2_cfg_7 r ln2_cs[1:0] - ln2_n[4:0] uuuuuuuu 0xuu 8 08h ln2_cfg_8 r - - - ln2_n?[4:0] uuuuuuuu 0xuu 9 09h ln2_cfg_9 r - - - ln2_s[4:0] uuuuuuuu 0xuu 10 0ah ln2_cfg_10 r ln2_hd - - ln2_cf[4:0] uuuuuuuu 0xuu 11 0bh ln2_cfg_11 r ln2_res1[7:0] uuuuuuuu 0xuu 12 0ch ln2_cfg_12 r ln2_res2[7:0] uuuuuuuu 0xuu 13 0dh ln2_cfg_13 r ln2_fchk[7:0] uuuuuuuu 0xuu 16 10h ln3_cfg_0 r ln3_did[7:0] uuuuuuuu 0xuu 17 11h ln3_cfg_1 r - - - - ln3_bid[3:0] uuuuuuuu 0xuu 18 12h ln3_cfg_2 r - - - ln3_lid[4:0] uuuuuuuu 0xuu 19 13h ln3_cfg_3 r ln3_scr - - ln3_l[4:0] uuuuuuuu 0xuu 20 14h ln3_cfg_4 r ln3_f[7:0] uuuuuuuu 0xuu 21 15h ln3_cfg_5 r - - - ln3_k[4:0] uuuuuuuu 0xuu 22 16h ln3_cfg_6 r ln3_m[7:0] uuuuuuuu 0xuu 23 17h ln3_cfg_7 r ln3_cs[1:0] - ln3_n[4:0] uuuuuuuu 0xuu 24 18h ln3_cfg_8 r - - - ln3_n?[4:0] uuuuuuuu 0xuu 25 19h ln3_cfg_9 r - - - ln3_s[4:0] uuuuuuuu 0xuu 26 1ah ln3_cfg_10 r ln3_hd - - ln3_cf[4:0] uuuuuuuu 0xuu 27 1bh ln3_cfg_11 r ln3_res1[7:0] uuuuuuuu 0xuu xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 84 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a [1] u = undefined at power-up or after reset. 28 1ch ln3_cfg_12 r ln3_res2[7:0] uuuuuuuu 0xuu 29 1dh ln3_cfg_13 r ln3_fchk[7:0] uuuuuuuu 0xuu 31 1fh page_address r/w - - - - - page[2:0] 00000000 00h table 173. page 7 register allocation map ?continued address register name r/w bit definition default [1] b7 b6 b5 b4 b3 b2 b1 b0 bin hex dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 85 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 10.15.2.14 page 7 bit defi nition detailed description please refer to ta b l e 1 7 3 for a register overview and thei r default values. in the following tables, all the values emphasized in bold are the default values. table 174. ln2_cfg_0 register (a ddress 00h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln2_did[7:0] r - lane 2 device id table 175. ln2_cfg_1 register (a ddress 01h) bit description default settings are shown highlighted. bit symbol access value description 3 to 0 ln2_bid[3:0] r - lane 2 bank id table 176. ln2_cfg_2 register (a ddress 02h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln2_lid[4:0] r - lane 2 lane id table 177. ln2_cfg_3 register (a ddress 03h) bit description default settings are shown highlighted. bit symbol access value description 7 ln2_scr r - scrambling on 4 to 0 ln2_l[4:0] r - number of lanes minus 1 table 178. ln2_cfg_4 register (a ddress 04h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln2_f[7:0] r - number of octets per frame minus 1 table 179. ln2_cfg_5 register (a ddress 05h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln2_k[4:0] r - number of frames per multiframe minus 1 table 180. ln2_cfg_6 register (a ddress 06h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln2_m[7:0] r - number of converters per device minus 1 table 181. ln2_cfg_7 register (a ddress 07h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ln2_cs[1:0] r - number of control bits 4 to 0 ln2_n[4:0] r - converter resolution minus 1 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 86 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 182. ln2_cfg_8 register (a ddress 08h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln2_n'[4:0] r - number of bits per sample minus 1 table 183. ln2_cfg_9 register (a ddress 09h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln2_s[4:0] r - number of samples per converter per frame cycle minus 1 table 184. ln2_cfg_10 register (a ddress 0ah) bit description default settings are shown highlighted. bit symbol access value description 7 ln2_hd r - high density 4 to 0 ln2_cf[4:0] r - number of control words per frame cycle table 185. ln2_cfg_11 register (address 0bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln2_res1[7:0] r - lane 2 reserved field table 186. ln2_cfg_12 register (a ddress 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln2_res2[7:0] r - lane 2 reserved field table 187. ln2_cfg_13 register (a ddress 0dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln2_fchk[7:0] r - lane 2 checksum table 188. ln3_cfg_0 register (a ddress 10h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln3_did[7:0] r - lane 3 device id table 189. ln3_cfg_1 register (address 11h) bit description default settings are shown highlighted. bit symbol access value description 3 to 0 ln3_bid[3:0] r - lane 3 bank id table 190. ln3_cfg_2 register (a ddress 12h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln3_lid[4:0] r - lane 3 lane id dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 87 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 191. ln3_cfg_3 register (a ddress 13h) bit description default settings are shown highlighted. bit symbol access value description 7 ln3_scr r - scrambling on 4 to 0 ln3_l[4:0] r - number of lanes minus 1 table 192. ln3_cfg_4 register (a ddress 14h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln3_f[7:0] r - number of octets per frame minus 1 table 193. ln3_cfg_5 register (a ddress 15h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln3_k[4:0] r - number of frames per multiframe minus 1 table 194. ln3_cfg_6 register (a ddress 16h) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln3_m[7:0] r - number of converters per device minus 1 table 195. ln3_cfg_7 register (a ddress 17h) bit description default settings are shown highlighted. bit symbol access value description 7 to 6 ln3_cs[1:0] r - number of control bits 4 to 0 ln3_n[4:0] r - converter resolution minus 1 table 196. ln3_cfg_8 register (a ddress 18h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln3_n'[4:0] r - number of bits per sample minus 1 table 197. ln3_cfg_9 register (a ddress 19h) bit description default settings are shown highlighted. bit symbol access value description 4 to 0 ln3_s[4:0] r - number of samples per converter per frame cycle minus 1 table 198. ln3_cfg_10 register (a ddress 1ah) bit description default settings are shown highlighted. bit symbol access value description 7 ln3_hd r - high density 4 to 0 ln3_cf[4:0] r - number of control words per frame cycle dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 88 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 199. ln3_cfg_11 register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln3_res1[7:0] r - lane 3 reserved field table 200. ln3_cfg_12 register (a ddress 1ch) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln3_res2[7:0] r - lane 3 reserved field table 201. ln3_cfg_13 register (a ddress 1dh) bit description default settings are shown highlighted. bit symbol access value description 7 to 0 ln3_fchk[7:0] r - lane 3 checksum table 202. page_address register (address 1fh) bit description default settings are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w 0h page_address dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 89 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 11. package outline fig 26. package outline sot804 (hvqfn64) references outline version european projection issue date iec jedec jeita sot804-3 - - - - - - - - - sot804-3_po unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.30 0.21 0.18 0.2 9.1 9.0 8.9 9.1 9.0 8.9 0.5 0.1 0.05 a dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. h vqfn64: plastic thermal enhanced very thin quad flat package; no leads; 6 4 terminals; body 9 x 9 x 0.85 mm sot804- 3 a 1 bcd (1) 0.1 y 1 d h 7.25 7.10 6.95 e (1) e h 7.25 7.10 6.95 ee 1 7.5 e 2 7.5 l 0.5 0.4 0.3 vw 0.05 y 0 2.5 5 mm scale terminal 1 index area terminal 1 index area b d a e b e 1 e a c b v c w 17 32 e 2 e 33 48 d h 49 64 e h l 1 16 c y c y 1 x detail x a 1 a c 1/2 e 1/2 e 09-02-24 10-08-06 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 90 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 12. abbreviations table 203. abbreviations acronym description aqm analog quadrature modulator ber bit error rate bw bandwidth cdi clock domain interface cdma code division multiple access cml current mode logic cmos complementary metal oxide semiconductor dac digital-to-analog converter dcsmu device configuration management and start-up unit des deserializer edge enhanced data rates for gsm evolution fir finite impulse response fpga field programmable gate array gsm global system for mobile communications if intermediate frequency ila inter-lane alignment imd3 third order intermodulation product lmds local multipoint distribution service lsb least significant bit lte long term evolution lvds low-voltage differential signaling mds multipoint distribution service mmds multichannel multipoint distribution service msb most significant bit nco numerically controlled oscillator nmos negative metal-oxide semiconductor pll phase-locked loop serdes serializer/deserializer sfdr spurious free dynamic range spi serial peripheral interface td-scdma time division-synchronous code division multiple access wcdma wideband code division multiple access wimax worldwide interoperability for microwave access dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 91 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 13. revision history table 204. revision history document id release date data sheet status change notice supersedes dac1008d650 v.2 20101217 product data sheet - dac1008d650 v.1 modifications: ? data sheet status changed from preliminary to product. ? text and drawings updated throughout entire data sheet. ? values in table 5 ? characteristics ? have been updated. ? section 10.2.2 ? sync and word align ? has been updated. ? table 142 ? code group synchronization state machine ? added to the data sheet. dac1008d650 v.1 20101001 preliminary data sheet - - dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 92 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request 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liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly 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all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 93 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 94 of 98 continued >> nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a 16. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 3. limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. thermal characteristics . . . . . . . . . . . . . . . . . . .6 table 5. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 6. digital layer processing latency . . . . . . . . . . .12 table 7. read or write mode access description . . . . .23 table 8. number of bytes to be transferred . . . . . . . . . .23 table 9. spi timing characteristic s . . . . . . . . . . . . . . . .24 table 10. interpolation filter coeffi cients . . . . . . . . . . . . .26 table 11. inversion filter coefficients . . . . . . . . . . . . . . . .28 table 12. dac transfer function . . . . . . . . . . . . . . . . . . .28 table 13. i o(fs) coarse adjustment . . . . . . . . . . . . . . . . . .30 table 14. i o(fs) fine adjustment . . . . . . . . . . . . . . . . . . . .30 table 15. digital offset adjustment . . . . . . . . . . . . . . . . .31 table 16. auxiliary dac transfer function . . . . . . . . . . . .32 table 17. page 0 register alloca tion map . . . . . . . . . . . .38 table 18. common register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 table 19. txcfg register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 table 20. pllcfg register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 table 21. freqnco_lsb register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 table 22. freqnco_lisb register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 table 23. freqnco_uisb register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 table 24. freqnco_msb register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 table 25. phinco_lsb r egister (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 table 26. phinco_msb register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 table 27. dac_a_cfg_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 table 28. dac_a_cfg_2 register (address 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 table 29. dac_a_cfg_3 register (address 0bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .42 table 30. dac_b_cfg_1 register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 table 31. dac_b_cfg_2 register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 table 32. dac_b_cfg_3 register (address 0eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43 table 33. dac_cfg register (address 0fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 34. dac_current_0 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 35. dac_current_1 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 36. dac_current_2 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 37. dac_current_3 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 38. dac_sel_ph_fine register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 39. phasecorr_cntrl0 register (address 16h) bit description . . . . . . . . . . . . . . 44 table 40. phasecorr_cntrl1 register (address 17h) bit description . . . . . . . . . . . . . . 44 table 41. dac_a_aux_msb register (address 1ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 42. dac_a_aux_lsb register (address 1bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 43. dac_b_aux_msb register (address 1ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 44. dac_b_aux_lsb register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 45. dac_b_aux_lsb register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 46. bias current control table . . . . . . . . . . . . . . . . . 45 table 47. page 1 register allocation map . . . . . . . . . . . . 46 table 48. mds_main register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 49. mds_win_period_a register (address 01h) bit description . . . . . . . . . . . . . . 47 table 50. mds_win_period_b register (address 02h) bit description . . . . . . . . . . . . . . 47 table 51. mds_misccntrl0 register (address 03h) bit description . . . . . . . . . . . . . . 48 table 52. mds_man_adjustdly register (address 04h) bit description . . . . . . . . . . . . . . 48 table 53. mds_auto_cycles register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 54. mds_misccntrl1 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 55. mds_adjdelay register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 56. mds_status0 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 57. mds_status1 register (address 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 58. page_address register (address 1fh) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 95 of 98 continued >> nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 table 59. page 2 register alloca tion map . . . . . . . . . . . .51 table 60. maincontrol r egister (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 61. jclk_cntrl register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 62. rst_ext_fclk register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 63. rst_ext_dclk register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 64. dcsmu_predivcnt register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 65. pll_chargetime register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 66. pll_run_in_time register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 67. ca_run_in_time register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 68. set_vcm_voltage register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 69. set_sync register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 70. type_id register (address 1bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 71. dac_version register (address 1ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 72. dig_version register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 73. jrx_ana_version register (address 1eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 74. page_address re gister (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 75. lane common-mode voltage adjustment . . . . .55 table 76. sync common-mode voltage adjustment . . . .55 table 77. sync swing voltage adjustment . . . . . . . . . . .55 table 78. page 4 register alloca tion map . . . . . . . . . . . .56 table 79. sr_dlp_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 table 80. sr_dlp_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 table 81. force_lock register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 table 82. man_lock_ln_1_0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 table 83. man_lock_2_0 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 table 84. ca_cntrl register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 table 85. scr_cntrl register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .60 table 86. ila_cntrl register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 87. force_align register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 88. man_align_ln_0_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 89. man_align_ln_2_3 register (address 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 90. fa_err_handling register (address 0bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 91. syncout_mode register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 92. lane_polarity register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 93. lane_select register (address 0eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 94. soft_reset_s crambler register (address 10h) bit description . . . . . . . . . . . . . . 64 table 95. init_scr_s15t8_ln0 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 96. init_scr_s7t1_ln0 (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 97. init_scr_s15t8_ln1 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 98. init_scr_s7t1_ln1 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 99. init_scr_s15t8_ln2 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 100. init_scr_s7t1_ln2 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 101. init_scr_s15t8_ln3 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 102. init_scr_s7t1_ln3 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 103. init_ila_bufptr_ln01 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 104. init_ila_bufptr_ln23 register (address 1ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 105. error_handling register (address 1bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 106. reinit_cntrl register (address 1ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 107. page_address re gister (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 108. page 5 register allocation map . . . . . . . . . . . . 68 table 109. ila_mon_1_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 110. ila_mon_3_2 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 111. ila_buf_err register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 112. ca_mon register (address 03h) dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 96 of 98 continued >> nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a bit description . . . . . . . . . . . . . . . . . . . . . . . . .70 table 113. dec_flags register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 table 114. kout_flag register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 table 115. k28_ln0_flag register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 table 116. k28_ln1_flag register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 table 117. k28_ln2_flag register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 table 118. k28_ln3_flag register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 table 119. kout_unexpected_flag register (address 0ah) bit description . . . . . . . . . . . . . .72 table 120. lock_cnt_mon_ln01 register (address 0bh) bit description . . . . . . . . . . . . . .72 table 121. lock_cnt_mon_ln23 register (address 0ch) bit description . . . . . . . . . . . . . .72 table 122. cs_state_lnx register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 table 123. rst_buf_err_flags register (address 0eh) bit description . . . . . . . . . . . . . .72 table 124. intr_misc_ena register (address 0fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 125. flag_cnt_lsb_ln0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 126. flag_cnt_msb_ln0 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 127. flag_cnt_lsb_ln1 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 128. flag_cnt_msb_ln1 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 129. flag_cnt_lsb_ln2 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 130. flag_cnt_msb_ln2 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 131. flag_cnt_lsb_ln3 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 132. flag_cnt_msb_ln3 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 table 133. ber_level_lsb register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 table 134. ber_level_msb register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 135. intr_ena register (address 1ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .74 table 136. cntrl_flagcnt_ln01 register (address 1bh) bit description . . . . . . . . . . . . . .75 table 137. cntrl_flagcnt_ln23 register (address 1ch) bit description . . . . . . . . . . . . . .75 table 138. mon_flags_reset register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 139. dbg_cntrl register (address 1eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 140. page_address re gister (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 141. counter source . . . . . . . . . . . . . . . . . . . . . . . . 76 table 142. code group synchronization state machine . . 76 table 143. page 6 register allocation map . . . . . . . . . . . . 77 table 144. ln0_cfg_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 145. ln0_cfg_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 146. ln0_cfg_2 register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 147. ln0_cfg_3 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 148. ln0_cfg_4 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 149. ln0_cfg_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 150. ln0_cfg_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 151. ln0_cfg_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 152. ln0_cfg_8 register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 153. ln0_cfg_9 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 154. ln0_cfg_10 register (address 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 155. ln0_cfg_11 register (address 0bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 156. ln0_cfg_12 register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 157. ln0_cfg_13 register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 158. ln1_cfg_0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 159. ln1_cfg_1 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 160. ln1_cfg_2 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 161. ln1_cfg_3 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 162. ln1_cfg_4 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 163. ln1_cfg_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 164. ln1_cfg_6 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 81 dac1008d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 17 december 2010 97 of 98 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a table 165. ln1_cfg_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 table 166. ln1_cfg_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 table 167. ln1_cfg_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 table 168. ln1_cfg_10 register (address 1ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81 table 169. ln1_cfg_11 register (address 1bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 table 170. ln1_cfg_12 register (address 1ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 table 171. ln1_cfg_13 register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 table 172. page_address register (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .82 table 173. page 7 register allocation map . . . . . . . . . . . .83 table 174. ln2_cfg_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 175. ln2_cfg_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 176. ln2_cfg_2 register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 177. ln2_cfg_3 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 178. ln2_cfg_4 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 179. ln2_cfg_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 180. ln2_cfg_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 181. ln2_cfg_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85 table 182. ln2_cfg_8 register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 183. ln2_cfg_9 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 184. ln2_cfg_10 register (address 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 185. ln2_cfg_11 register (address 0bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 186. ln2_cfg_12 register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 187. ln2_cfg_13 register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 188. ln3_cfg_0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 189. ln3_cfg_1 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 190. ln3_cfg_2 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86 table 191. ln3_cfg_3 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .87 table 192. ln3_cfg_4 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .87 table 193. ln3_cfg_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .87 table 194. ln3_cfg_6 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 195. ln3_cfg_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 196. ln3_cfg_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 197. ln3_cfg_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 198. ln3_cfg_10 register (address 1ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 199. ln3_cfg_11 register (address 1bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 200. ln3_cfg_12 register (address 1ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 201. ln3_cfg_13 register (address 1dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 202. page_address re gister (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 203. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 204. revision history . . . . . . . . . . . . . . . . . . . . . . . 91 nxp semiconductors dac1008d650 2 , 4 or 8 interpolating dac with jesd204a ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 december 2010 document identifier: dac1008d650 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 thermal characteristics . . . . . . . . . . . . . . . . . . 6 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 application information. . . . . . . . . . . . . . . . . . 11 10.1 general description . . . . . . . . . . . . . . . . . . . . 11 10.2 jesd204a receiver . . . . . . . . . . . . . . . . . . . . 12 10.2.1 lane input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10.2.2 sync and word align . . . . . . . . . . . . . . . . . . . . 13 10.2.3 comma detection and word align . . . . . . . . . . 14 10.2.4 descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.2.5 inter-lane alignment . . . . . . . . . . . . . . . . . . . . 15 10.2.5.1 single device operation . . . . . . . . . . . . . . . . . 15 10.2.5.2 multi-device operation . . . . . . . . . . . . . . . . . . 15 10.2.5.3 master/slave mode . . . . . . . . . . . . . . . . . . . . . 17 10.2.5.4 all slave mode . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2.6 frame assembly . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 serial peripheral interfac e (spi) . . . . . . . . . . . 23 10.3.1 protocol description . . . . . . . . . . . . . . . . . . . . 23 10.3.2 spi timing description . . . . . . . . . . . . . . . . . . . 24 10.4 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.5 fir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.6 quadrature modulator and numerically controlled oscillator (nco) . . . . . . . . . . . . . . 27 10.6.1 nco in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.6.2 low-power nco . . . . . . . . . . . . . . . . . . . . . . . 27 10.6.3 minus_3db . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.7 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.8 dac transfer function . . . . . . . . . . . . . . . . . . . 28 10.9 full-scale current . . . . . . . . . . . . . . . . . . . . . . 29 10.9.1 regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.9.1.1 external regulation . . . . . . . . . . . . . . . . . . . . . 29 10.9.2 full-scale current adjustment . . . . . . . . . . . . . 29 10.10 digital offset correction . . . . . . . . . . . . . . . . . . 30 10.11 analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.12 auxiliary dacs . . . . . . . . . . . . . . . . . . . . . . . . 32 10.13 output configuration . . . . . . . . . . . . . . . . . . . . 33 10.13.1 basic output configuration . . . . . . . . . . . . . . . 33 10.13.2 dc interface to an analog quadrature modulator (aqm) . . . . . . . . . . . . . . . . . . . . . . 34 10.13.3 ac interface to an analog quadrature modulator (aqm) . . . . . . . . . . . . . . . . . . . . . . 36 10.13.4 phase correction . . . . . . . . . . . . . . . . . . . . . . 37 10.14 power and grounding. . . . . . . . . . . . . . . . . . . 37 10.15 configuration interface. . . . . . . . . . . . . . . . . . 37 10.15.1 register description . . . . . . . . . . . . . . . . . . . . 37 10.15.2 detailed descriptions of registers . . . . . . . . . . 37 10.15.2.1 page 0 allocation map description . . . . . . . . . 38 10.15.2.2 page 0 bit definition detailed description . . . . 40 10.15.2.3 page 1 allocation map description . . . . . . . . . 46 10.15.2.4 page 1 bit definition detailed description . . . . 47 10.15.2.5 page 2 allocation map description . . . . . . . . . 51 10.15.2.6 page 2 bit definition detailed description . . . . 52 10.15.2.7 page 4 allocation map description . . . . . . . . . 56 10.15.2.8 page 4 bit definition detailed description . . . . 58 10.15.2.9 page 5 allocation map description . . . . . . . . . 68 10.15.2.10 page 5 bit definition detailed description . . . 70 10.15.2.11 page 6 allocation ma p description . . . . . . . . 77 10.15.2.12 page 6 bit definition detailed description . . . 79 10.15.2.13 page 7 allocation map description . . . . . . . . 83 10.15.2.14 page 7 bit definition detailed description . . . 85 11 package outline. . . . . . . . . . . . . . . . . . . . . . . . 89 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90 13 revision history . . . . . . . . . . . . . . . . . . . . . . . 91 14 legal information . . . . . . . . . . . . . . . . . . . . . . 92 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 92 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93 15 contact information . . . . . . . . . . . . . . . . . . . . 93 16 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 |
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